diff options
| author | Fuad Tabba <tabba@google.com> | 2021-05-24 11:29:55 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2021-05-25 21:27:49 +0300 |
| commit | 814b186079cd54d3fe3b6b8ab539cbd44705ef9d (patch) | |
| tree | c2433f7dff0bb3a36a2425f38429a7e12b84ced2 /arch/arm64/kernel/smp_spin_table.c | |
| parent | 163d3f80695e31068c7d32244c9e6d406d5c5c00 (diff) | |
| download | linux-814b186079cd54d3fe3b6b8ab539cbd44705ef9d.tar.xz | |
arm64: __flush_dcache_area to take end parameter instead of size
To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.
No functional change intended.
Reported-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-13-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/kernel/smp_spin_table.c')
| -rw-r--r-- | arch/arm64/kernel/smp_spin_table.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm64/kernel/smp_spin_table.c b/arch/arm64/kernel/smp_spin_table.c index c45a83512805..58d804582a35 100644 --- a/arch/arm64/kernel/smp_spin_table.c +++ b/arch/arm64/kernel/smp_spin_table.c @@ -36,7 +36,7 @@ static void write_pen_release(u64 val) unsigned long size = sizeof(secondary_holding_pen_release); secondary_holding_pen_release = val; - __flush_dcache_area(start, size); + __flush_dcache_area((unsigned long)start, (unsigned long)start + size); } @@ -90,8 +90,9 @@ static int smp_spin_table_cpu_prepare(unsigned int cpu) * the boot protocol. */ writeq_relaxed(pa_holding_pen, release_addr); - __flush_dcache_area((__force void *)release_addr, - sizeof(*release_addr)); + __flush_dcache_area((__force unsigned long)release_addr, + (__force unsigned long)release_addr + + sizeof(*release_addr)); /* * Send an event to wake up the secondary CPU. |