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| author | Ingo Molnar <mingo@kernel.org> | 2018-02-11 13:33:33 +0300 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2018-02-11 13:33:33 +0300 |
| commit | 7980033bea8a74692fdb987c44ec91b0be8e752b (patch) | |
| tree | 02b57329465d397b3a20468a683e56d1cda88cf6 /arch/arm64/mm/cache.S | |
| parent | 3197b04bb39b596613ff2f8143c5cd0a6908debf (diff) | |
| parent | f1517df8701c9f12dae9ce7f43a5d300a6917619 (diff) | |
| download | linux-7980033bea8a74692fdb987c44ec91b0be8e752b.tar.xz | |
Merge branch 'linus' into x86/urgent, to pick up dependent commits
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/arm64/mm/cache.S')
| -rw-r--r-- | arch/arm64/mm/cache.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 7f1dbe962cf5..91464e7f77cc 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -49,7 +49,7 @@ ENTRY(flush_icache_range) * - end - virtual end address of region */ ENTRY(__flush_cache_user_range) - uaccess_ttbr0_enable x2, x3 + uaccess_ttbr0_enable x2, x3, x4 dcache_line_size x2, x3 sub x3, x2, #1 bic x4, x0, x3 @@ -72,7 +72,7 @@ USER(9f, ic ivau, x4 ) // invalidate I line PoU isb mov x0, #0 1: - uaccess_ttbr0_disable x1 + uaccess_ttbr0_disable x1, x2 ret 9: mov x0, #-EFAULT |