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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-11-03 13:14:07 +0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-01-05 16:57:08 +0400
commit8390918874324360335370fbcc2c3c9884476884 (patch)
treeca6fa695d29445b8427f247905565d58bdd59ed1 /arch/arm
parent4045407fd7740642b18bc802e8bab064e79a61e5 (diff)
downloadlinux-8390918874324360335370fbcc2c3c9884476884.tar.xz
ARM: restart: remove s3c24xx restart handler
Remove the s3c24xx restart handler, which is trying to work around a chip bug by keeping caches on but flushed. As we now only disable caches when performing a soft reboot, there doesn't need to be a work-around to do that. Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c23
1 files changed, 0 insertions, 23 deletions
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 3c6335307fb1..1121df13e15f 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -192,27 +192,6 @@ static unsigned long s3c24xx_read_idcode_v4(void)
return __raw_readl(S3C2410_GSTATUS1);
}
-/* Hook for arm_pm_restart to ensure we execute the reset code
- * with the caches enabled. It seems at least the S3C2440 has a problem
- * resetting if there is bus activity interrupted by the reset.
- */
-static void s3c24xx_pm_restart(char mode, const char *cmd)
-{
- if (mode != 's') {
- unsigned long flags;
-
- local_irq_save(flags);
- __cpuc_flush_kern_all();
- __cpuc_flush_user_all();
-
- arch_reset(mode, cmd);
- local_irq_restore(flags);
- }
-
- /* fallback, or unhandled */
- arm_machine_restart(mode, cmd);
-}
-
void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
{
/* initialise the io descriptors we need for initialisation */
@@ -226,7 +205,5 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
}
s3c24xx_init_cpu();
- arm_pm_restart = s3c24xx_pm_restart;
-
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
}