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author | Christoph Hellwig <hch@lst.de> | 2022-02-23 10:47:20 +0300 |
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committer | Christoph Hellwig <hch@lst.de> | 2022-02-23 10:52:50 +0300 |
commit | 1c4b5ecb7ea190fa3e9f9d6891e6c90b60e04f24 (patch) | |
tree | a9444a92909dc4929e0d1e42301e1d3dbd16c35c /arch/h8300/boot/dts/h8s_sim.dts | |
parent | 5c1ee569660d4a205dced9cb4d0306b907fb7599 (diff) | |
download | linux-1c4b5ecb7ea190fa3e9f9d6891e6c90b60e04f24.tar.xz |
remove the h8300 architecture
Signed-off-by: Christoph Hellwig <hch@lst.de>
Diffstat (limited to 'arch/h8300/boot/dts/h8s_sim.dts')
-rw-r--r-- | arch/h8300/boot/dts/h8s_sim.dts | 100 |
1 files changed, 0 insertions, 100 deletions
diff --git a/arch/h8300/boot/dts/h8s_sim.dts b/arch/h8300/boot/dts/h8s_sim.dts deleted file mode 100644 index 932cc3c5a81b..000000000000 --- a/arch/h8300/boot/dts/h8s_sim.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; -/ { - compatible = "gnu,gdbsim"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&h8intc>; - - chosen { - bootargs = "earlyprintk=h8300-sim"; - stdout-path = <&sci0>; - }; - aliases { - serial0 = &sci0; - serial1 = &sci1; - }; - - xclk: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "xtal"; - }; - pllclk: pllclk { - compatible = "renesas,h8s2678-pll-clock"; - clocks = <&xclk>; - #clock-cells = <0>; - reg = <0xfee03b 2>, <0xfee045 2>; - }; - core_clk: core_clk { - compatible = "renesas,h8300-div-clock"; - clocks = <&pllclk>; - #clock-cells = <0>; - reg = <0xfee03b 2>; - renesas,width = <3>; - }; - fclk: fclk { - compatible = "fixed-factor-clock"; - clocks = <&core_clk>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - - memory@400000 { - device_type = "memory"; - reg = <0x400000 0x800000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "renesas,h8300"; - clock-frequency = <33333333>; - }; - }; - - h8intc: interrupt-controller@fffe00 { - compatible = "renesas,h8s-intc", "renesas,h8300-intc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xfffe00 24>; - }; - - bsc: memory-controller@fffec0 { - compatible = "renesas,h8s-bsc", "renesas,h8300-bsc"; - reg = <0xfffec0 24>; - }; - - tpu: timer@ffffe0 { - compatible = "renesas,tpu"; - reg = <0xffffe0 16>, <0xfffff0 12>; - clocks = <&fclk>; - clock-names = "fck"; - }; - - timer8: timer@ffffb0 { - compatible = "renesas,8bit-timer"; - reg = <0xffffb0 10>; - interrupts = <72 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; - - sci0: serial@ffff78 { - compatible = "renesas,sci"; - reg = <0xffff78 8>; - interrupts = <88 0>, <89 0>, <90 0>, <91 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; - sci1: serial@ffff80 { - compatible = "renesas,sci"; - reg = <0xffff80 8>; - interrupts = <92 0>, <93 0>, <94 0>, <95 0>; - clocks = <&fclk>; - clock-names = "fck"; - }; -}; |