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authorGreg Ungerer <gerg@uclinux.org>2009-03-24 10:22:05 +0300
committerGreg Ungerer <gerg@uclinux.org>2009-03-24 10:37:57 +0300
commit9242ef12f0d174da1739a071fb4a5fc5de27905e (patch)
tree9451acce18ff78069f42e2959f4b2fe205bb5fef /arch/m68knommu
parentd62db60659416499b763a00c953f23ed1c9a5c46 (diff)
downloadlinux-9242ef12f0d174da1739a071fb4a5fc5de27905e.tar.xz
m68knommu: fix 5307 ColdFire UART vector setup
There is a couple of problems with the UART vector setup for the 5307 ColdFire UART. The ICR register access should be 8bit, not 32bit. The address of the UIVR register is wrong, it needs to be offset into the MBAR register region. Fix these. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu')
-rw-r--r--arch/m68knommu/platform/5307/config.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/m68knommu/platform/5307/config.c b/arch/m68knommu/platform/5307/config.c
index 724faf05852a..44803bf70a6e 100644
--- a/arch/m68knommu/platform/5307/config.c
+++ b/arch/m68knommu/platform/5307/config.c
@@ -65,12 +65,12 @@ static struct platform_device *m5307_devices[] __initdata = {
static void __init m5307_uart_init_line(int line, int irq)
{
if (line == 0) {
- writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
- writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
+ writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+ writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
} else if (line == 1) {
- writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
- writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
+ writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+ writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
}
}