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authorAppana Durga Kedareswara rao <appana.durga.rao@xilinx.com>2022-06-27 09:40:23 +0300
committerMichal Simek <michal.simek@amd.com>2022-09-26 15:13:28 +0300
commit88707ebe77e23e856981e597f322cabbf6415662 (patch)
treec6a93fc52d836473454d1f17619f9a47f3bd050e /arch/microblaze/kernel/asm-offsets.c
parenta5e3aaa654c15760afdfb85d0b6fd825ce068efc (diff)
downloadlinux-88707ebe77e23e856981e597f322cabbf6415662.tar.xz
microblaze: Add custom break vector handler for mb manager
When the TMR Manager detects a fault Lockstep state it is signaled to the MicroBlaze processors by asserting a break signal, When Microblaze gets a break vector from tmr Microblaze it's needed to clear/block the break bit in the tmr manager before performing recovery. In order to perform recovery need to perform the following steps. 1) Store all internal MicroBlaze registers in RAM 2) Execute a suspend instruction which asserts the reset signal 3) Restore all registers from RAM and execute an RTBD instruction to return from the reset handler, to resume execution at the place where the break occurred. This API supports getting called from kernel space only. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Link: https://lore.kernel.org/r/20220627064024.771037-3-appana.durga.rao@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'arch/microblaze/kernel/asm-offsets.c')
-rw-r--r--arch/microblaze/kernel/asm-offsets.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/microblaze/kernel/asm-offsets.c b/arch/microblaze/kernel/asm-offsets.c
index 47ee409508b1..104c3ac5f30c 100644
--- a/arch/microblaze/kernel/asm-offsets.c
+++ b/arch/microblaze/kernel/asm-offsets.c
@@ -120,5 +120,12 @@ int main(int argc, char *argv[])
DEFINE(CC_FSR, offsetof(struct cpu_context, fsr));
BLANK();
+ /* struct cpuinfo */
+ DEFINE(CI_DCS, offsetof(struct cpuinfo, dcache_size));
+ DEFINE(CI_DCL, offsetof(struct cpuinfo, dcache_line_length));
+ DEFINE(CI_ICS, offsetof(struct cpuinfo, icache_size));
+ DEFINE(CI_ICL, offsetof(struct cpuinfo, icache_line_length));
+ BLANK();
+
return 0;
}