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authorMichal Simek <monstr@monstr.eu>2009-10-08 15:06:42 +0400
committerMichal Simek <monstr@monstr.eu>2009-12-14 10:44:57 +0300
commit44e4e196a9b3a703ebe273ffe3fb6cda326fe5d3 (patch)
tree1e9217c3af95f1843dbe499cd7022fd531ef4c38 /arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
parent6cec713b1629228527fb8f813003522817f55da1 (diff)
downloadlinux-44e4e196a9b3a703ebe273ffe3fb6cda326fe5d3.tar.xz
microblaze: Fix cache_line_lenght
We used cache_line as cache_line_lenght. For this reason we did cache flushing 4 times longer than was necessary. Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c')
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
index c259786e7faa..c5acf2b56eed 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
@@ -70,7 +70,7 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
CI(use_icache, USE_ICACHE);
CI(icache_tagbits, ICACHE_ADDR_TAG_BITS);
CI(icache_write, ICACHE_ALLOW_WR);
- CI(icache_line, ICACHE_LINE_LEN);
+ ci->icache_line_length = PVR_ICACHE_LINE_LEN(pvr) << 2;
CI(icache_size, ICACHE_BYTE_SIZE);
CI(icache_base, ICACHE_BASEADDR);
CI(icache_high, ICACHE_HIGHADDR);
@@ -78,7 +78,7 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
CI(use_dcache, USE_DCACHE);
CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS);
CI(dcache_write, DCACHE_ALLOW_WR);
- CI(dcache_line, DCACHE_LINE_LEN);
+ ci->dcache_line_length = PVR_DCACHE_LINE_LEN(pvr) << 2;
CI(dcache_size, DCACHE_BYTE_SIZE);
CI(dcache_base, DCACHE_BASEADDR);
CI(dcache_high, DCACHE_HIGHADDR);