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authorRalf Baechle <ralf@linux-mips.org>2008-09-16 21:48:51 +0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 19:18:52 +0400
commit384740dc49ea651ba350704d13ff6be9976e37fe (patch)
treea6e80cad287ccae7a86d81bfa692fc96889c88ed /arch/mips/include/asm/asmmacro.h
parente8c7c482347574ecdd45c43e32c332d5fc2ece61 (diff)
downloadlinux-384740dc49ea651ba350704d13ff6be9976e37fe.tar.xz
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/asmmacro.h')
-rw-r--r--arch/mips/include/asm/asmmacro.h82
1 files changed, 82 insertions, 0 deletions
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
new file mode 100644
index 000000000000..7a881755800f
--- /dev/null
+++ b/arch/mips/include/asm/asmmacro.h
@@ -0,0 +1,82 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef _ASM_ASMMACRO_H
+#define _ASM_ASMMACRO_H
+
+#include <asm/hazards.h>
+
+#ifdef CONFIG_32BIT
+#include <asm/asmmacro-32.h>
+#endif
+#ifdef CONFIG_64BIT
+#include <asm/asmmacro-64.h>
+#endif
+#ifdef CONFIG_MIPS_MT_SMTC
+#include <asm/mipsmtregs.h>
+#endif
+
+#ifdef CONFIG_MIPS_MT_SMTC
+ .macro local_irq_enable reg=t0
+ mfc0 \reg, CP0_TCSTATUS
+ ori \reg, \reg, TCSTATUS_IXMT
+ xori \reg, \reg, TCSTATUS_IXMT
+ mtc0 \reg, CP0_TCSTATUS
+ _ehb
+ .endm
+
+ .macro local_irq_disable reg=t0
+ mfc0 \reg, CP0_TCSTATUS
+ ori \reg, \reg, TCSTATUS_IXMT
+ mtc0 \reg, CP0_TCSTATUS
+ _ehb
+ .endm
+#else
+ .macro local_irq_enable reg=t0
+ mfc0 \reg, CP0_STATUS
+ ori \reg, \reg, 1
+ mtc0 \reg, CP0_STATUS
+ irq_enable_hazard
+ .endm
+
+ .macro local_irq_disable reg=t0
+ mfc0 \reg, CP0_STATUS
+ ori \reg, \reg, 1
+ xori \reg, \reg, 1
+ mtc0 \reg, CP0_STATUS
+ irq_disable_hazard
+ .endm
+#endif /* CONFIG_MIPS_MT_SMTC */
+
+/*
+ * Temporary until all gas have MT ASE support
+ */
+ .macro DMT reg=0
+ .word 0x41600bc1 | (\reg << 16)
+ .endm
+
+ .macro EMT reg=0
+ .word 0x41600be1 | (\reg << 16)
+ .endm
+
+ .macro DVPE reg=0
+ .word 0x41600001 | (\reg << 16)
+ .endm
+
+ .macro EVPE reg=0
+ .word 0x41600021 | (\reg << 16)
+ .endm
+
+ .macro MFTR rt=0, rd=0, u=0, sel=0
+ .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
+ .endm
+
+ .macro MTTR rt=0, rd=0, u=0, sel=0
+ .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
+ .endm
+
+#endif /* _ASM_ASMMACRO_H */