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authorRalf Baechle <ralf@linux-mips.org>2013-01-22 15:59:30 +0400
committerRalf Baechle <ralf@linux-mips.org>2013-02-01 13:00:22 +0400
commit7034228792cc561e79ff8600f02884bd4c80e287 (patch)
tree89b77af37d087d9de236fc5d21f60bf552d0a2c6 /arch/mips/include/asm/netlogic/xlp-hal/iomap.h
parent405ab01c70e18058d9c01a1256769a61fc65413e (diff)
downloadlinux-7034228792cc561e79ff8600f02884bd4c80e287.tar.xz
MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/netlogic/xlp-hal/iomap.h')
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h48
1 files changed, 24 insertions, 24 deletions
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 2c63f9754640..9fac46fb7913 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -35,12 +35,12 @@
#ifndef __NLM_HAL_IOMAP_H__
#define __NLM_HAL_IOMAP_H__
-#define XLP_DEFAULT_IO_BASE 0x18000000
+#define XLP_DEFAULT_IO_BASE 0x18000000
#define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE
#define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000
#define NMI_BASE 0xbfc00000
-#define XLP_IO_CLK 133333333
+#define XLP_IO_CLK 133333333
#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
@@ -96,8 +96,8 @@
#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
/* SD flash */
-#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
-#define XLP_IO_MMC_OFFSET(node, slot) \
+#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
+#define XLP_IO_MMC_OFFSET(node, slot) \
((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
/* PCI config header register id's */
@@ -125,26 +125,26 @@
#define XLP_PCI_SBB_WT_REG 0x3f
/* PCI IDs for SoC device */
-#define PCI_VENDOR_NETLOGIC 0x184e
-
-#define PCI_DEVICE_ID_NLM_ROOT 0x1001
-#define PCI_DEVICE_ID_NLM_ICI 0x1002
-#define PCI_DEVICE_ID_NLM_PIC 0x1003
-#define PCI_DEVICE_ID_NLM_PCIE 0x1004
-#define PCI_DEVICE_ID_NLM_EHCI 0x1007
-#define PCI_DEVICE_ID_NLM_OHCI 0x1008
-#define PCI_DEVICE_ID_NLM_NAE 0x1009
-#define PCI_DEVICE_ID_NLM_POE 0x100A
-#define PCI_DEVICE_ID_NLM_FMN 0x100B
-#define PCI_DEVICE_ID_NLM_RAID 0x100D
-#define PCI_DEVICE_ID_NLM_SAE 0x100D
-#define PCI_DEVICE_ID_NLM_RSA 0x100E
-#define PCI_DEVICE_ID_NLM_CMP 0x100F
-#define PCI_DEVICE_ID_NLM_UART 0x1010
-#define PCI_DEVICE_ID_NLM_I2C 0x1011
-#define PCI_DEVICE_ID_NLM_NOR 0x1015
-#define PCI_DEVICE_ID_NLM_NAND 0x1016
-#define PCI_DEVICE_ID_NLM_MMC 0x1018
+#define PCI_VENDOR_NETLOGIC 0x184e
+
+#define PCI_DEVICE_ID_NLM_ROOT 0x1001
+#define PCI_DEVICE_ID_NLM_ICI 0x1002
+#define PCI_DEVICE_ID_NLM_PIC 0x1003
+#define PCI_DEVICE_ID_NLM_PCIE 0x1004
+#define PCI_DEVICE_ID_NLM_EHCI 0x1007
+#define PCI_DEVICE_ID_NLM_OHCI 0x1008
+#define PCI_DEVICE_ID_NLM_NAE 0x1009
+#define PCI_DEVICE_ID_NLM_POE 0x100A
+#define PCI_DEVICE_ID_NLM_FMN 0x100B
+#define PCI_DEVICE_ID_NLM_RAID 0x100D
+#define PCI_DEVICE_ID_NLM_SAE 0x100D
+#define PCI_DEVICE_ID_NLM_RSA 0x100E
+#define PCI_DEVICE_ID_NLM_CMP 0x100F
+#define PCI_DEVICE_ID_NLM_UART 0x1010
+#define PCI_DEVICE_ID_NLM_I2C 0x1011
+#define PCI_DEVICE_ID_NLM_NOR 0x1015
+#define PCI_DEVICE_ID_NLM_NAND 0x1016
+#define PCI_DEVICE_ID_NLM_MMC 0x1018
#ifndef __ASSEMBLY__