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authorDavid Daney <ddaney@caviumnetworks.com>2009-10-14 23:16:56 +0400
committerRalf Baechle <ralf@linux-mips.org>2009-12-17 04:57:01 +0300
commit82622284dd2f8791f9759f3cef601520a8bc63b2 (patch)
treeee47f43af373d0c021cc83ff9e22925942e9d001 /arch/mips/include/asm/stackframe.h
parent92078e0618f525e22945040b5daea21d4b6d4a16 (diff)
downloadlinux-82622284dd2f8791f9759f3cef601520a8bc63b2.tar.xz
MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors.
Processors that support the mips64r2 ISA can in four instructions convert a shifted PGD pointer stored in the upper bits of c0_context into a usable pointer. By doing this we save a memory load and associated potential cache miss in the TLB exception handlers. Since the upper bits of c0_context were holding the CPU number, we move this to the upper bits of c0_xcontext which doesn't have enough bits to hold the PGD pointer, but has plenty for the CPU number. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/stackframe.h')
-rw-r--r--arch/mips/include/asm/stackframe.h20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index dd7e220e087b..3b6da3330e32 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -87,15 +87,19 @@
#ifdef CONFIG_SMP
#ifdef CONFIG_MIPS_MT_SMTC
#define PTEBASE_SHIFT 19 /* TCBIND */
+#define CPU_ID_REG CP0_TCBIND
+#define CPU_ID_MFC0 mfc0
+#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
+#define PTEBASE_SHIFT 48 /* XCONTEXT */
+#define CPU_ID_REG CP0_XCONTEXT
+#define CPU_ID_MFC0 MFC0
#else
#define PTEBASE_SHIFT 23 /* CONTEXT */
+#define CPU_ID_REG CP0_CONTEXT
+#define CPU_ID_MFC0 MFC0
#endif
.macro get_saved_sp /* SMP variation */
-#ifdef CONFIG_MIPS_MT_SMTC
- mfc0 k0, CP0_TCBIND
-#else
- MFC0 k0, CP0_CONTEXT
-#endif
+ CPU_ID_MFC0 k0, CPU_ID_REG
#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
lui k1, %hi(kernelsp)
#else
@@ -111,11 +115,7 @@
.endm
.macro set_saved_sp stackp temp temp2
-#ifdef CONFIG_MIPS_MT_SMTC
- mfc0 \temp, CP0_TCBIND
-#else
- MFC0 \temp, CP0_CONTEXT
-#endif
+ CPU_ID_MFC0 \temp, CPU_ID_REG
LONG_SRL \temp, PTEBASE_SHIFT
LONG_S \stackp, kernelsp(\temp)
.endm