summaryrefslogtreecommitdiff
path: root/arch/mips/include/asm/switch_to.h
diff options
context:
space:
mode:
authorMarkos Chandras <markos.chandras@imgtec.com>2014-12-03 15:37:32 +0300
committerMarkos Chandras <markos.chandras@imgtec.com>2015-02-17 18:37:37 +0300
commit7c151d3d5d7a032e08dbe86ad6088622391bf13e (patch)
tree362d5ffcf8fea7c26373750efb106ca1e41c275f /arch/mips/include/asm/switch_to.h
parentb0a668fb2038d846a466c7a16a358d874002b697 (diff)
downloadlinux-7c151d3d5d7a032e08dbe86ad6088622391bf13e.tar.xz
MIPS: Make use of the ERETNC instruction on MIPS R6
The ERETNC instruction, introduced in MIPS R5, is similar to the ERET one, except it does not clear the LLB bit in the LLADDR register. This feature is necessary to safely emulate R2 LL/SC instructions. However, on context switches, we need to clear the LLAddr/LLB bit in order to make sure that an SC instruction from the new thread will never succeed if it happens to interrupt an LL operation on the same address from the previous thread. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/include/asm/switch_to.h')
-rw-r--r--arch/mips/include/asm/switch_to.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index b928b6f898cd..e92d6c4b5ed1 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -75,9 +75,12 @@ do { \
#endif
#define __clear_software_ll_bit() \
-do { \
- if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \
- ll_bit = 0; \
+do { if (cpu_has_rw_llb) { \
+ write_c0_lladdr(0); \
+ } else { \
+ if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc)\
+ ll_bit = 0; \
+ } \
} while (0)
#define switch_to(prev, next, last) \