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| author | 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> | 2020-09-22 04:24:44 +0300 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-27 11:58:10 +0300 |
| commit | a5ce852398a4efc9df4869a71ff45b9dda58882d (patch) | |
| tree | 2c37f74f1639dbd61a73eb8ae9bf6fcd20067fb6 /arch/mips/mm/cerr-sb1.c | |
| parent | a9fee3a513e560b154ccbe662faa791d5f358875 (diff) | |
| download | linux-a5ce852398a4efc9df4869a71ff45b9dda58882d.tar.xz | |
MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.
1.Fix bugs when detecting ways value of JZ4775's L2 cache.
2.Fix bugs when detecting sets value and ways value of X1000E's L2 cache.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/mm/cerr-sb1.c')
0 files changed, 0 insertions, 0 deletions