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| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-14 19:05:00 +0300 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-15 11:40:29 +0300 |
| commit | 564c836fd945a94b5dd46597d6b7adb464092650 (patch) | |
| tree | 1c8500388f9aada05ebd9958f2b26b30c72b132f /arch/mips/sni | |
| parent | baf5cb30fbd1c22f6aa03c081794c2ee0f5be4da (diff) | |
| download | linux-564c836fd945a94b5dd46597d6b7adb464092650.tar.xz | |
MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.
Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/sni')
0 files changed, 0 insertions, 0 deletions