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authorJustin Swartz <justin.swartz@risingedge.co.za>2024-03-08 18:56:15 +0300
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2024-03-11 15:58:06 +0300
commit82394085bf0368a2b2ab9c41d3a5cebf05cff02e (patch)
tree6955b230d4404357d4a24c0079eb1eb6633acb15 /arch/mips
parentbc75dffadc063eb46200611cc41d1e2373219e11 (diff)
downloadlinux-82394085bf0368a2b2ab9c41d3a5cebf05cff02e.tar.xz
mips: dts: ralink: mt7621: reorder serial0 properties
Reorder serial0 properties according to the guidelines laid out in Documentation/devicetree/bindings/dts-coding-style.rst Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za> Reviewed-by: Arınç ÜNAL <arinc.unal@arinc9.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/boot/dts/ralink/mt7621.dtsi5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index dca415fddd90..68467fca3fc9 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -115,13 +115,14 @@
compatible = "ns16550a";
reg = <0xc00 0x100>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
clocks = <&sysc MT7621_CLK_UART1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
no-loopback-test;
pinctrl-names = "default";