diff options
| author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2017-03-22 06:36:58 +0300 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-04-01 13:12:20 +0300 |
| commit | 957b778a166e32e242a33fdab693ffb256a19cbd (patch) | |
| tree | e4ffce7347a62e55ac2cd99b3efdb2e62c7cf070 /arch/powerpc/include/asm/book3s/64/mmu-hash.h | |
| parent | f6eedbba7a26fdaee9ea8121336dc86236c136c7 (diff) | |
| download | linux-957b778a166e32e242a33fdab693ffb256a19cbd.tar.xz | |
powerpc/mm: Add addr_limit to mm_context and use it to derive max slice index
In the followup patch, we will increase the slice array size to handle
512TB range, but will limit the max addr to 128TB. Avoid doing
unnecessary computation and avoid doing slice mask related operation
above address limit.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/book3s/64/mmu-hash.h')
| -rw-r--r-- | arch/powerpc/include/asm/book3s/64/mmu-hash.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/book3s/64/mmu-hash.h b/arch/powerpc/include/asm/book3s/64/mmu-hash.h index c93450bf306f..5961b0d65a79 100644 --- a/arch/powerpc/include/asm/book3s/64/mmu-hash.h +++ b/arch/powerpc/include/asm/book3s/64/mmu-hash.h @@ -597,7 +597,8 @@ extern void slb_set_size(u16 size); #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT)) /* 4 bits per slice and we have one slice per 1TB */ -#define SLICE_ARRAY_SIZE (H_PGTABLE_RANGE >> 41) +#define SLICE_ARRAY_SIZE (H_PGTABLE_RANGE >> 41) +#define TASK_SLICE_ARRAY_SZ(x) ((x)->context.addr_limit >> 41) #ifndef __ASSEMBLY__ |