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| author | Athira Rajeev <atrajeev@linux.vnet.ibm.com> | 2021-03-04 14:55:37 +0300 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2021-04-22 18:38:02 +0300 |
| commit | b4ded42268ee3d703da208278342b9901abe145a (patch) | |
| tree | 2b620af7dff153a6bc909bb18c116268a9f12421 /arch/powerpc/perf/isa207-common.h | |
| parent | 0bd3f9e953bd3636e73d296e9bed11a25c09c118 (diff) | |
| download | linux-b4ded42268ee3d703da208278342b9901abe145a.tar.xz | |
powerpc/perf: Fix sampled instruction type for larx/stcx
Sampled Instruction Event Register (SIER) field [46:48] identifies the
sampled instruction type. ISA v3.1 says value of 0b111 for this field as
reserved, but in POWER10 it denotes LARX/STCX type which will hopefully
be fixed in ISA v3.1 update.
Patch fixes the functions to handle type value 7 for CPU_FTR_ARCH_31.
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: Madhavan Srinivasan <maddy@linux.ibm.com>
[mpe: Avoid reading mmcra until necessary, use early return to deindent if block]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1614858937-1485-1-git-send-email-atrajeev@linux.vnet.ibm.com
Diffstat (limited to 'arch/powerpc/perf/isa207-common.h')
| -rw-r--r-- | arch/powerpc/perf/isa207-common.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h index ae8d44e325c7..4a2cbc3dc047 100644 --- a/arch/powerpc/perf/isa207-common.h +++ b/arch/powerpc/perf/isa207-common.h @@ -220,6 +220,7 @@ /* Bits in MMCRA for PowerISA v2.07 */ #define MMCRA_SAMP_MODE_SHIFT 1 #define MMCRA_SAMP_ELIG_SHIFT 4 +#define MMCRA_SAMP_ELIG_MASK 7 #define MMCRA_THR_CTL_SHIFT 8 #define MMCRA_THR_SEL_SHIFT 16 #define MMCRA_THR_CMP_SHIFT 32 |