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author | Paolo Bonzini <pbonzini@redhat.com> | 2023-07-01 14:02:41 +0300 |
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committer | Paolo Bonzini <pbonzini@redhat.com> | 2023-07-01 14:02:41 +0300 |
commit | b5396271eab4ec28f0d27ff48e1b151b7b824295 (patch) | |
tree | e14349ab2ce6be6c8b77d3a52a8d330f85ee181b /arch/riscv/include/asm/kvm_aia_imsic.h | |
parent | a443e2609c01479c7c0c3367059d7b9f2e8a6697 (diff) | |
parent | 07f225b5842420ae9c18cba17873fc71ed69c28e (diff) | |
download | linux-b5396271eab4ec28f0d27ff48e1b151b7b824295.tar.xz |
Merge tag 'kvm-riscv-6.5-1' of https://github.com/kvm-riscv/linux into HEAD
KVM/riscv changes for 6.5
- Redirect AMO load/store misaligned traps to KVM guest
- Trap-n-emulate AIA in-kernel irqchip for KVM guest
- Svnapot support for KVM Guest
Diffstat (limited to 'arch/riscv/include/asm/kvm_aia_imsic.h')
-rw-r--r-- | arch/riscv/include/asm/kvm_aia_imsic.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/kvm_aia_imsic.h b/arch/riscv/include/asm/kvm_aia_imsic.h new file mode 100644 index 000000000000..da5881d2bde0 --- /dev/null +++ b/arch/riscv/include/asm/kvm_aia_imsic.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ +#ifndef __KVM_RISCV_AIA_IMSIC_H +#define __KVM_RISCV_AIA_IMSIC_H + +#include <linux/types.h> +#include <asm/csr.h> + +#define IMSIC_MMIO_PAGE_SHIFT 12 +#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT) +#define IMSIC_MMIO_PAGE_LE 0x00 +#define IMSIC_MMIO_PAGE_BE 0x04 + +#define IMSIC_MIN_ID 63 +#define IMSIC_MAX_ID 2048 + +#define IMSIC_EIDELIVERY 0x70 + +#define IMSIC_EITHRESHOLD 0x72 + +#define IMSIC_EIP0 0x80 +#define IMSIC_EIP63 0xbf +#define IMSIC_EIPx_BITS 32 + +#define IMSIC_EIE0 0xc0 +#define IMSIC_EIE63 0xff +#define IMSIC_EIEx_BITS 32 + +#define IMSIC_FIRST IMSIC_EIDELIVERY +#define IMSIC_LAST IMSIC_EIE63 + +#define IMSIC_MMIO_SETIPNUM_LE 0x00 +#define IMSIC_MMIO_SETIPNUM_BE 0x04 + +#endif |