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| author | Frederik Haxel <haxel@fzi.de> | 2023-12-12 16:01:13 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-01-10 06:33:21 +0300 |
| commit | 5daa3726410288075ba73c336bb2e80d6b06aa4d (patch) | |
| tree | a1451f18f991c636ba19215a0a5ae7c4c3da52e1 /arch/riscv | |
| parent | 66f1e68093979816a23412a3fad066f5bcbc0360 (diff) | |
| download | linux-5daa3726410288075ba73c336bb2e80d6b06aa4d.tar.xz | |
riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro
During the refactoring, a bug was introduced in the rarly used
XIP_FIXUP_FLASH_OFFSET macro.
Fixes: bee7fbc38579 ("RISC-V CPU Idle Support")
Fixes: e7681beba992 ("RISC-V: Split out the XIP fixups into their own file")
Signed-off-by: Frederik Haxel <haxel@fzi.de>
Link: https://lore.kernel.org/r/20231212130116.848530-3-haxel@fzi.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/include/asm/xip_fixup.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/xip_fixup.h b/arch/riscv/include/asm/xip_fixup.h index d4ffc3c37649..b65bf6306f69 100644 --- a/arch/riscv/include/asm/xip_fixup.h +++ b/arch/riscv/include/asm/xip_fixup.h @@ -13,7 +13,7 @@ add \reg, \reg, t0 .endm .macro XIP_FIXUP_FLASH_OFFSET reg - la t1, __data_loc + la t0, __data_loc REG_L t1, _xip_phys_offset sub \reg, \reg, t1 add \reg, \reg, t0 |