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| author | Peter Zijlstra <peterz@infradead.org> | 2022-05-10 22:22:04 +0300 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-05-18 01:08:25 +0300 |
| commit | 3c27b0c6ea48bc61492a138c410e262735d660ab (patch) | |
| tree | facfef5bda5b0cf88f172f5dd25309f1964e8ad9 /arch/x86/events/amd/core.c | |
| parent | bc469ddf67154a4840267132e87ce0d8b72d4952 (diff) | |
| download | linux-3c27b0c6ea48bc61492a138c410e262735d660ab.tar.xz | |
perf/x86/amd: Fix AMD BRS period adjustment
There's two problems with the current amd_brs_adjust_period() code:
- it isn't in fact AMD specific and wil always adjust the period;
- it adjusts the period, while it should only adjust the event count,
resulting in repoting a short period.
Fix this by using x86_pmu.limit_period, this makes it specific to the
AMD BRS case and ensures only the event count is adjusted while the
reported period is unmodified.
Fixes: ba2fe7500845 ("perf/x86/amd: Add AMD branch sampling period adjustment")
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Diffstat (limited to 'arch/x86/events/amd/core.c')
| -rw-r--r-- | arch/x86/events/amd/core.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index d81eac2284ea..3eee59c64daa 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -1255,6 +1255,18 @@ static void amd_pmu_sched_task(struct perf_event_context *ctx, amd_pmu_brs_sched_task(ctx, sched_in); } +static u64 amd_pmu_limit_period(struct perf_event *event, u64 left) +{ + /* + * Decrease period by the depth of the BRS feature to get the last N + * taken branches and approximate the desired period + */ + if (has_branch_stack(event) && left > x86_pmu.lbr_nr) + left -= x86_pmu.lbr_nr; + + return left; +} + static __initconst const struct x86_pmu amd_pmu = { .name = "AMD", .handle_irq = amd_pmu_handle_irq, @@ -1415,6 +1427,7 @@ static int __init amd_core_pmu_init(void) if (boot_cpu_data.x86 >= 0x19 && !amd_brs_init()) { x86_pmu.get_event_constraints = amd_get_event_constraints_f19h; x86_pmu.sched_task = amd_pmu_sched_task; + x86_pmu.limit_period = amd_pmu_limit_period; /* * put_event_constraints callback same as Fam17h, set above */ |