diff options
| author | Kan Liang <kan.liang@linux.intel.com> | 2021-07-01 00:08:26 +0300 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2021-07-02 16:58:37 +0300 |
| commit | 949b11381f81664df3997db2ae0ec9546ab6dd85 (patch) | |
| tree | eaa6cf1a464f9e3cedd905fe56b7a95e056c3b48 /arch/x86/events/intel/uncore_discovery.c | |
| parent | c54c53d9921adef2c239cb43d5a936b63c57ebf0 (diff) | |
| download | linux-949b11381f81664df3997db2ae0ec9546ab6dd85.tar.xz | |
perf/x86/intel/uncore: Add Sapphire Rapids server CHA support
CHA merges the caching agent and Home Agent (HA) responsibilities of the
chip into a single block. It's one of the Sapphire Rapids server uncore
units.
The layout of the control registers for a CHA uncore unit is a little
bit different from the generic one. The CHA uncore unit also supports a
filter register for TID. So a specific format and ops are required.
Expose the common MSR ops which can be reused.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-3-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events/intel/uncore_discovery.c')
| -rw-r--r-- | arch/x86/events/intel/uncore_discovery.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/intel/uncore_discovery.c index 93148e215bbc..25f1c0157078 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -337,17 +337,17 @@ static const struct attribute_group generic_uncore_format_group = { .attrs = generic_uncore_formats_attr, }; -static void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box) +void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box) { wrmsrl(uncore_msr_box_ctl(box), GENERIC_PMON_BOX_CTL_INT); } -static void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box) +void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box) { wrmsrl(uncore_msr_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ); } -static void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box) +void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box) { wrmsrl(uncore_msr_box_ctl(box), 0); } |