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authorThomas Gleixner <tglx@linutronix.de>2020-02-12 02:34:01 +0300
committerBorislav Petkov <bp@suse.de>2020-04-14 16:47:11 +0300
commitc9bf318f77b3a78483e656e609d005c52aadc86d (patch)
tree475b6e6950ba1387736445e93c261621e2ab6513 /arch/x86/kernel/cpu/mce/internal.h
parentada018b15ccecbdb95df46db7121516edb906bf6 (diff)
downloadlinux-c9bf318f77b3a78483e656e609d005c52aadc86d.tar.xz
x86/mce/amd: Init thresholding machinery only on relevant vendors
... and not unconditionally. [ bp: Add a new vendor_flags bit for that. ] Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200403161943.1458-3-bp@alien8.de
Diffstat (limited to 'arch/x86/kernel/cpu/mce/internal.h')
-rw-r--r--arch/x86/kernel/cpu/mce/internal.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h
index 3b008172ad73..74a01829c4f4 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -148,7 +148,7 @@ struct mce_vendor_flags {
* Recovery. It indicates support for data poisoning in HW and deferred
* error interrupts.
*/
- succor : 1,
+ succor : 1,
/*
* (AMD) SMCA: This bit indicates support for Scalable MCA which expands
@@ -156,9 +156,12 @@ struct mce_vendor_flags {
* banks. Also, to accommodate the new banks and registers, the MCA
* register space is moved to a new MSR range.
*/
- smca : 1,
+ smca : 1,
- __reserved_0 : 61;
+ /* AMD-style error thresholding banks present. */
+ amd_threshold : 1,
+
+ __reserved_0 : 60;
};
extern struct mce_vendor_flags mce_flags;