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authorIngo Molnar <mingo@kernel.org>2021-03-18 17:28:01 +0300
committerIngo Molnar <mingo@kernel.org>2021-03-18 17:31:53 +0300
commitd9f6e12fb0b7fcded0bac34b8293ec46f80dfc33 (patch)
tree5c4f4fbfc0c8554c5f158ab499890a6b29188402 /arch/x86/kernel/cpu/resctrl/core.c
parent14ff3ed86e2c1700345f411b90a78f62867f217e (diff)
downloadlinux-d9f6e12fb0b7fcded0bac34b8293ec46f80dfc33.tar.xz
x86: Fix various typos in comments
Fix ~144 single-word typos in arch/x86/ code comments. Doing this in a single commit should reduce the churn. Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'arch/x86/kernel/cpu/resctrl/core.c')
-rw-r--r--arch/x86/kernel/cpu/resctrl/core.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 698bb26aeb6e..23001ae03e82 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -192,7 +192,7 @@ static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid)
* Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz
* Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz
*
- * Probe by trying to write the first of the L3 cach mask registers
+ * Probe by trying to write the first of the L3 cache mask registers
* and checking that the bits stick. Max CLOSids is always 4 and max cbm length
* is always 20 on hsw server parts. The minimum cache bitmask length
* allowed for HSW server is always 2 bits. Hardcode all of them.