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authorLike Xu <likexu@tencent.com>2022-06-01 06:19:24 +0300
committerPaolo Bonzini <pbonzini@redhat.com>2022-06-08 20:06:17 +0300
commit6ef25aa0a961298278301ae1d88106c701eb73fa (patch)
treebd57de8db47e08927d016a4153d9f707a09dfe76 /arch/x86/kvm/pmu.h
parentb9181c8ef35636152facc72f801f27b4264df8c0 (diff)
downloadlinux-6ef25aa0a961298278301ae1d88106c701eb73fa.tar.xz
KVM: x86/pmu: Restrict advanced features based on module enable_pmu
Once vPMU is disabled, the KVM would not expose features like: PEBS (via clear kvm_pmu_cap.pebs_ept), legacy LBR and ARCH_LBR, CPUID 0xA leaf, PDCM bit and MSR_IA32_PERF_CAPABILITIES, plus PT_MODE_HOST_GUEST mode. What this group of features has in common is that their use relies on the underlying PMU counter and the host perf_event as a back-end resource requester or sharing part of the irq delivery path. Signed-off-by: Like Xu <likexu@tencent.com> Message-Id: <20220601031925.59693-2-likexu@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/kvm/pmu.h')
-rw-r--r--arch/x86/kvm/pmu.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h
index 2c5b3c9f5531..c1b61671ba1e 100644
--- a/arch/x86/kvm/pmu.h
+++ b/arch/x86/kvm/pmu.h
@@ -170,9 +170,11 @@ static inline void kvm_init_pmu_capability(void)
* For Intel, only support guest architectural pmu
* on a host with architectural pmu.
*/
- if ((is_intel && !kvm_pmu_cap.version) || !kvm_pmu_cap.num_counters_gp) {
- memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap));
+ if ((is_intel && !kvm_pmu_cap.version) || !kvm_pmu_cap.num_counters_gp)
enable_pmu = false;
+
+ if (!enable_pmu) {
+ memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap));
return;
}