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authorEmil Renner Berthing <emil.renner.berthing@canonical.com>2023-07-22 17:36:17 +0300
committerEmil Renner Berthing <emil.renner.berthing@canonical.com>2024-05-08 12:38:24 +0300
commit076836e772e24f316e3bab01586c55f0954bf2d9 (patch)
treeed5883865b454de6487776710a38ad443bde4ac9 /arch
parent584eedcdfd92ac7293a3badb28bc74288334d7fe (diff)
downloadlinux-076836e772e24f316e3bab01586c55f0954bf2d9.tar.xz
riscv: dts: starfive: Add JH7100 USB node
Add the device tree node for the USB 3.0 peripheral on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/riscv/boot/dts/starfive/jh7100-common.dtsi5
-rw-r--r--arch/riscv/boot/dts/starfive/jh7100.dtsi26
2 files changed, 31 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index 1f79481bfd96..3fad20c55dc3 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -447,3 +447,8 @@
pinctrl-0 = <&uart3_pins>;
status = "okay";
};
+
+&usb3 {
+ dr_mode = "host";
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 0216a32bbff4..bfe3ff40d953 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -255,6 +255,32 @@
#reset-cells = <1>;
};
+ usb3: usb@104c0000 {
+ compatible = "starfive,jh7100-usb";
+ ranges = <0x0 0x0 0x104c0000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&audclk JH7100_AUDCLK_USB_LPM>,
+ <&audclk JH7100_AUDCLK_USB_STB>,
+ <&clkgen JH7100_CLK_USB_AXI>,
+ <&clkgen JH7100_CLK_USBNOC_AXI>;
+ clock-names = "lpm", "stb", "axi", "nocaxi";
+ resets = <&rstgen JH7100_RSTN_USB_AXI>,
+ <&rstgen JH7100_RSTN_USBNOC_AXI>;
+ reset-names = "axi", "nocaxi";
+ status = "disabled";
+
+ usb_cdns3: usb@0 {
+ compatible = "cdns,usb3";
+ reg = <0x00000 0x10000>,
+ <0x10000 0x10000>,
+ <0x20000 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <44>, <52>, <43>;
+ interrupt-names = "host", "peripheral", "otg";
+ };
+ };
+
clkgen: clock-controller@11800000 {
compatible = "starfive,jh7100-clkgen";
reg = <0x0 0x11800000 0x0 0x10000>;