Merge branch 'pm-cpufreq'

Merge cpufreq changes for 6.2-rc1:

 - Generalize of_perf_domain_get_sharing_cpumask phandle format (Hector
   Martin).

 - Add new cpufreq driver for Apple SoC CPU P-states (Hector Martin).

 - Update Qualcomm cpufreq driver, including:
   * CPU clock provider support,
   * Generic cleanups or reorganization.
   * Potential memleak fix.
   * Fix of the return value of cpufreq_driver->get().
   (Manivannan Sadhasivam, Chen Hui).

 - Update Qualcomm cpufreq driver's DT bindings, including:
   * Support for CPU clock provider.
   * Missing cache-related properties fixes.
   * Support for QDU1000/QRU1000.
   (Manivannan Sadhasivam, Rob Herring, Melody Olvera).

 - Add support for ti,am625 SoC and enable build of ti-cpufreq for
   ARCH_K3 (Dave Gerlach, and Vibhore Vardhan).

 - Use flexible array to simplify memory allocation in the tegra186
   cpufreq driver (Christophe JAILLET).

 - Convert cpufreq statistics code to use sysfs_emit_at() (ye xingchen).

 - Allow intel_pstate to use no-HWP mode on Sapphire Rapids (Giovanni
   Gherdovich).

 - Add missing pci_dev_put() to the amd_freq_sensitivity cpufreq driver
   (Xiongfeng Wang).

 - Initialize the kobj_unregister completion before calling
   kobject_init_and_add() in the cpufreq core code (Yongqiang Liu).

 - Defer setting boost MSRs in the ACPI cpufreq driver (Stuart Hayes,
   Nathan Chancellor).

 - Make intel_pstate accept initial EPP value of 0x80 (Srinivas
   Pandruvada).

 - Make read-only array sys_clk_src in the SPEAr cpufreq driver static
   (Colin Ian King).

 - Make array speeds in the longhaul cpufreq driver static (Colin Ian
   King).

 - Use str_enabled_disabled() helper in the ACPI cpufreq driver (Andy
   Shevchenko).

 - Drop a reference to CVS from cpufreq documentation (Conghui Wang).

* pm-cpufreq: (30 commits)
  cpufreq: Remove CVS version control contents from documentation
  cpufreq: stats: Convert to use sysfs_emit_at() API
  cpufreq: ACPI: Only set boost MSRs on supported CPUs
  dt-bindings: cpufreq: cpufreq-qcom-hw: Add QDU1000/QRU1000 cpufreq
  cpufreq: tegra186: Use flexible array to simplify memory allocation
  cpufreq: intel_pstate: Add Sapphire Rapids support in no-HWP mode
  cpufreq: amd_freq_sensitivity: Add missing pci_dev_put()
  cpufreq: Init completion before kobject_init_and_add()
  cpufreq: apple-soc: Add new driver to control Apple SoC CPU P-states
  cpufreq: qcom-hw: Add CPU clock provider support
  dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider
  cpufreq: qcom-hw: Fix the frequency returned by cpufreq_driver->get()
  cpufreq: ACPI: Remove unused variables 'acpi_cpufreq_online' and 'ret'
  cpufreq: qcom-hw: Fix memory leak in qcom_cpufreq_hw_read_lut()
  arm64: dts: ti: k3-am625-sk: Add 1.4GHz OPP
  cpufreq: ti: Enable ti-cpufreq for ARCH_K3
  arm64: dts: ti: k3-am625: Introduce operating-points table
  cpufreq: dt-platdev: Blacklist ti,am625 SoC
  cpufreq: ti-cpufreq: Add support for AM625
  dt-bindings: cpufreq: qcom: Add missing cache related properties
  ...

2 files changed, 60 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
index 93a5f0817efc..4620ef5e19bb 100644
--- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
@@ -31,6 +31,15 @@
 		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
 	};
 
+	opp-table {
+		/* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
+		opp-1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-supported-hw = <0x01 0x0004>;
+			clock-latency-ns = <6000000>;
+		};
+	};
+
 	memory@80000000 {
 		device_type = "memory";
 		/* 2G RAM */
diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi
index 887f31c23fef..cea2cc7de5dd 100644
--- a/arch/arm64/boot/dts/ti/k3-am625.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi
@@ -48,6 +48,8 @@
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&L2_0>;
+			operating-points-v2 = <&a53_opp_table>;
+			clocks = <&k3_clks 135 0>;
 		};
 
 		cpu1: cpu@1 {
@@ -62,6 +64,8 @@
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&L2_0>;
+			operating-points-v2 = <&a53_opp_table>;
+			clocks = <&k3_clks 136 0>;
 		};
 
 		cpu2: cpu@2 {
@@ -76,6 +80,8 @@
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&L2_0>;
+			operating-points-v2 = <&a53_opp_table>;
+			clocks = <&k3_clks 137 0>;
 		};
 
 		cpu3: cpu@3 {
@@ -90,6 +96,51 @@
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&L2_0>;
+			operating-points-v2 = <&a53_opp_table>;
+			clocks = <&k3_clks 138 0>;
+		};
+	};
+
+	a53_opp_table: opp-table {
+		compatible = "operating-points-v2-ti-cpu";
+		opp-shared;
+		syscon = <&wkup_conf>;
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-supported-hw = <0x01 0x0007>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-supported-hw = <0x01 0x0007>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-supported-hw = <0x01 0x0007>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-supported-hw = <0x01 0x0007>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-supported-hw = <0x01 0x0006>;
+			clock-latency-ns = <6000000>;
+		};
+
+		opp-1250000000 {
+			opp-hz = /bits/ 64 <1250000000>;
+			opp-supported-hw = <0x01 0x0004>;
+			clock-latency-ns = <6000000>;
+			opp-suspend;
 		};
 	};