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authorLinus Torvalds <torvalds@linux-foundation.org>2021-07-10 19:22:44 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2021-07-10 19:22:44 +0300
commit6e207b882159ed3e35a4cd4ff0fc155cce5e3cbc (patch)
treeb33ae527de0082a3448365d8bc51f4fe8338fedd /arch
parentb6fd9e259457b847646844ed202b830e585289dd (diff)
parent42accadb3265f4569620cde217ff448b568b2822 (diff)
downloadlinux-6e207b882159ed3e35a4cd4ff0fc155cce5e3cbc.tar.xz
Merge tag 'arm-soc-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC updates from Olof Johansson: "A few SoC (code) changes have queued up this cycle, mostly for minor changes and some refactoring and cleanup of legacy platforms. This branch also contains a few of the fixes that weren't sent in by the end of the release (all fairly minor). - Adding an additional maintainer for the TEE subsystem (Sumit Garg) - Quite a significant modernization of the IXP4xx platforms by Linus Walleij, revisiting with a new PCI host driver/binding, removing legacy mach/* include dependencies and moving platform detection/config to drivers/soc. Also some updates/cleanup of platform data. - Core power domain support for Tegra platforms, and some improvements in build test coverage by adding stubs for compile test targets. - A handful of updates to i.MX platforms, adding legacy (non-PSCI) SMP support on i.MX7D, SoC ID setup for i.MX50, removal of platform data and board fixups for iMX6/7. ... and a few smaller changes and fixes for Samsung, OMAP, Allwinner, Rockchip" * tag 'arm-soc-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (53 commits) MAINTAINERS: Add myself as TEE subsystem reviewer ixp4xx: fix spelling mistake in Kconfig "Devce" -> "Device" hw_random: ixp4xx: Add OF support hw_random: ixp4xx: Add DT bindings hw_random: ixp4xx: Turn into a module hw_random: ixp4xx: Use SPDX license tag hw_random: ixp4xx: enable compile-testing pata: ixp4xx: split platform data to its own header soc: ixp4xx: move cpu detection to linux/soc/ixp4xx/cpu.h PCI: ixp4xx: Add a new driver for IXP4xx PCI: ixp4xx: Add device tree bindings for IXP4xx ARM/ixp4xx: Make NEED_MACH_IO_H optional ARM/ixp4xx: Move the virtual IObases MAINTAINERS: ARM/MStar/Sigmastar SoCs: Add a link to the MStar tree ARM: debug: add UART early console support for MSTAR SoCs ARM: dts: ux500: Fix LED probing ARM: imx: add smp support for imx7d ARM: imx6q: drop of_platform_default_populate() from init_machine arm64: dts: rockchip: Update RK3399 PCI host bridge window to 32-bit address memory soc/tegra: fuse: Fix Tegra234-only builds ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig3
-rw-r--r--arch/arm/Kconfig.debug15
-rw-r--r--arch/arm/boot/dts/am5718.dtsi6
-rw-r--r--arch/arm/boot/dts/dra7-l4.dtsi22
-rw-r--r--arch/arm/boot/dts/dra71x.dtsi4
-rw-r--r--arch/arm/boot/dts/dra72x.dtsi4
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi92
-rw-r--r--arch/arm/boot/dts/qcom-sdx55-t55.dts2
-rw-r--r--arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts4
-rw-r--r--arch/arm/boot/dts/ste-href.dtsi7
-rw-r--r--arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts2
-rw-r--r--arch/arm/mach-exynos/exynos.c2
-rw-r--r--arch/arm/mach-imx/Makefile2
-rw-r--r--arch/arm/mach-imx/common.h3
-rw-r--r--arch/arm/mach-imx/headsmp.S9
-rw-r--r--arch/arm/mach-imx/hotplug.c3
-rw-r--r--arch/arm/mach-imx/mach-imx50.c7
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c88
-rw-r--r--arch/arm/mach-imx/mach-imx6sx.c26
-rw-r--r--arch/arm/mach-imx/mach-imx7d.c25
-rw-r--r--arch/arm/mach-imx/platsmp.c26
-rw-r--r--arch/arm/mach-imx/src.c101
-rw-r--r--arch/arm/mach-imx/suspend-imx53.S4
-rw-r--r--arch/arm/mach-ixp4xx/Kconfig35
-rw-r--r--arch/arm/mach-ixp4xx/avila-setup.c1
-rw-r--r--arch/arm/mach-ixp4xx/common.c47
-rw-r--r--arch/arm/mach-ixp4xx/fsg-setup.c1
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/cpu.h54
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h61
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/platform.h14
-rw-r--r--arch/arm/mach-ixp4xx/ixp4xx-of.c8
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-setup.c1
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-setup.c1
-rw-r--r--arch/arm/mach-omap1/Kconfig12
-rw-r--r--arch/arm/mach-omap2/cm.h1
-rw-r--r--arch/arm/mach-omap2/cm_common.c13
-rw-r--r--arch/arm/mach-omap2/common.h1
-rw-r--r--arch/arm/mach-omap2/control.c5
-rw-r--r--arch/arm/mach-omap2/control.h1
-rw-r--r--arch/arm/mach-omap2/pm33xx-core.c40
-rw-r--r--arch/arm/mach-s3c/mach-rx1950.c1
-rw-r--r--arch/arm64/Kconfig.platforms1
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts2
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi2
45 files changed, 354 insertions, 407 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 06b6187b67af..3ea1c417339f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -394,7 +394,8 @@ config ARCH_IXP4XX
select HAVE_PCI
select IXP4XX_IRQ
select IXP4XX_TIMER
- select NEED_MACH_IO_H
+ # With the new PCI driver this is not needed
+ select NEED_MACH_IO_H if PCI_IXP4XX_LEGACY
select USB_EHCI_BIG_ENDIAN_DESC
select USB_EHCI_BIG_ENDIAN_MMIO
help
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 7902bc2096e0..1c4384db223d 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -609,6 +609,14 @@ choice
when u-boot hands over to the kernel, the system
silently crashes, with no serial output at all.
+ config DEBUG_MSTARV7_PMUART
+ bool "Kernel low-level debugging messages via MSTARV7 PM UART"
+ depends on ARCH_MSTARV7
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ for MSTAR ARMv7-based platforms on PM UART.
+
config DEBUG_MT6589_UART0
bool "Mediatek mt6589 UART0"
depends on ARCH_MEDIATEK
@@ -1607,6 +1615,7 @@ config DEBUG_UART_PHYS
default 0x18000400 if DEBUG_BCM_HR2
default 0x18023000 if DEBUG_BCM_IPROC_UART3
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
+ default 0x1f221000 if DEBUG_MSTARV7_PMUART
default 0x20001000 if DEBUG_HIP01_UART
default 0x20060000 if DEBUG_RK29_UART0
default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
@@ -1724,6 +1733,7 @@ config DEBUG_UART_VIRT
default 0xf0100000 if DEBUG_DIGICOLOR_UA0
default 0xf01fb000 if DEBUG_NOMADIK_UART
default 0xf0201000 if DEBUG_BCM2835 || DEBUG_BCM2836
+ default 0xf0221000 if DEBUG_MSTARV7_PMUART
default 0xf1000300 if DEBUG_BCM_5301X
default 0xf1000400 if DEBUG_BCM_HR2
default 0xf1002000 if DEBUG_MT8127_UART0
@@ -1805,8 +1815,8 @@ config DEBUG_UART_VIRT
default 0xfedc0000 if DEBUG_EP93XX
default 0xfee003f8 if DEBUG_FOOTBRIDGE_COM1
default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
- default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
- default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
+ default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
+ default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
default 0xfef36000 if DEBUG_HIGHBANK_UART
default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
@@ -1829,6 +1839,7 @@ config DEBUG_UART_8250_SHIFT
default 0 if DEBUG_FOOTBRIDGE_COM1 || ARCH_IOP32X || DEBUG_BCM_5301X || \
DEBUG_BCM_HR2 || DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || \
DEBUG_OMAP7XXUART3
+ default 3 if DEBUG_MSTARV7_PMUART
default 2
config DEBUG_UART_8250_WORD
diff --git a/arch/arm/boot/dts/am5718.dtsi b/arch/arm/boot/dts/am5718.dtsi
index ebf4d3cc1cfb..6d7530a48c73 100644
--- a/arch/arm/boot/dts/am5718.dtsi
+++ b/arch/arm/boot/dts/am5718.dtsi
@@ -17,17 +17,13 @@
* VCP1, VCP2
* MLB
* ISS
- * USB3, USB4
+ * USB3
*/
&usb3_tm {
status = "disabled";
};
-&usb4_tm {
- status = "disabled";
-};
-
&atl_tm {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index 149144cdff35..648d23f7f748 100644
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -4129,28 +4129,6 @@
};
};
- usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x140000 0x4>,
- <0x140010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x140000 0x20000>;
- };
-
target-module@170000 { /* 0x48970000, ap 21 0a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x170010 0x4>;
diff --git a/arch/arm/boot/dts/dra71x.dtsi b/arch/arm/boot/dts/dra71x.dtsi
index cad0e4a2bd8d..9c270d8f75d5 100644
--- a/arch/arm/boot/dts/dra71x.dtsi
+++ b/arch/arm/boot/dts/dra71x.dtsi
@@ -11,7 +11,3 @@
&rtctarget {
status = "disabled";
};
-
-&usb4_tm {
- status = "disabled";
-};
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index d403acc754b6..f3e934ef7d3e 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -108,7 +108,3 @@
&pcie2_rc {
compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
};
-
-&usb4_tm {
- status = "disabled";
-};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index e1850d6c841a..b4e07d99ffde 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -49,49 +49,6 @@
reg = <0x41500000 0x100>;
};
- target-module@48940000 {
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x48940000 0x4>,
- <0x48940010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x48940000 0x20000>;
-
- omap_dwc3_4: omap_dwc3_4@0 {
- compatible = "ti,dwc3";
- reg = <0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <1>;
- utmi-mode = <2>;
- ranges;
- status = "disabled";
- usb4: usb@10000 {
- compatible = "snps,dwc3";
- reg = <0x10000 0x17000>;
- interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "peripheral",
- "host",
- "otg";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- };
- };
- };
target-module@41501000 {
compatible = "ti,sysc-omap2", "ti,sysc";
@@ -224,3 +181,52 @@
&pcie2_rc {
compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
};
+
+&l4_per3 {
+ segment@0 {
+ usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x140000 0x4>,
+ <0x140010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x140000 0x20000>;
+
+ omap_dwc3_4: omap_dwc3_4@0 {
+ compatible = "ti,dwc3";
+ reg = <0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ status = "disabled";
+ usb4: usb@10000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000 0x17000>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts
index ddcd53aa533d..2ffcd085904d 100644
--- a/arch/arm/boot/dts/qcom-sdx55-t55.dts
+++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts
@@ -250,7 +250,7 @@
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
/* efs2 partition is secured */
- secure-regions = <0x500000 0xb00000>;
+ secure-regions = /bits/ 64 <0x500000 0xb00000>;
};
};
diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
index 3065f84634b8..80c40da79604 100644
--- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
+++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
@@ -250,8 +250,8 @@
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
/* ico and efs2 partitions are secured */
- secure-regions = <0x500000 0x500000
- 0xa00000 0xb00000>;
+ secure-regions = /bits/ 64 <0x500000 0x500000
+ 0xa00000 0xb00000>;
};
};
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 83b179692dff..13d216192904 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
#include "ste-href-family-pinctrl.dtsi"
/ {
@@ -64,17 +65,20 @@
reg = <0>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
linux,default-trigger = "heartbeat";
};
chan@1 {
reg = <1>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
chan@2 {
reg = <2>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
};
lp5521@34 {
@@ -88,16 +92,19 @@
reg = <0>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
chan@1 {
reg = <1>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
chan@2 {
reg = <2>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
};
bh1780@29 {
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index 97f497854e05..d05fa679dcd3 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -85,7 +85,7 @@
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
};
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 25b01da4771b..8b48326be9fd 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -55,6 +55,7 @@ void __init exynos_sysram_init(void)
sysram_base_addr = of_iomap(node, 0);
sysram_base_phys = of_translate_address(node,
of_get_address(node, 0, NULL, NULL));
+ of_node_put(node);
break;
}
@@ -62,6 +63,7 @@ void __init exynos_sysram_init(void)
if (!of_device_is_available(node))
continue;
sysram_ns_base_addr = of_iomap(node, 0);
+ of_node_put(node);
break;
}
}
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 9cebd360d58e..d1506ef7a537 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -35,7 +35,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
-ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7D_CA7)$(CONFIG_SOC_LS1021A),)
AFLAGS_headsmp.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 474dedb73bc7..f0a073a71401 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -68,11 +68,13 @@ void imx_set_cpu_arg(int cpu, u32 arg);
void v7_secondary_startup(void);
void imx_scu_map_io(void);
void imx_smp_prepare(void);
+void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn);
#else
static inline void imx_scu_map_io(void) {}
static inline void imx_smp_prepare(void) {}
#endif
void imx_src_init(void);
+void imx7_src_init(void);
void imx_gpc_pre_suspend(bool arm_power_off);
void imx_gpc_post_resume(void);
void imx_gpc_mask_all(void);
@@ -131,6 +133,7 @@ static inline void imx_init_l2cache(void) {}
#endif
extern const struct smp_operations imx_smp_ops;
+extern const struct smp_operations imx7_smp_ops;
extern const struct smp_operations ls1021a_smp_ops;
#endif
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 766dbdb2ae27..fcba58be8e79 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -21,6 +21,15 @@ diag_reg_offset:
ENTRY(v7_secondary_startup)
ARM_BE8(setend be) @ go BE8 if entered LE
+ mrc p15, 0, r0, c0, c0, 0
+ lsl r0, r0, #16
+ lsr r0, r0, #20
+ /* 0xc07 is cortex A7's ID */
+ mov r1, #0xc00
+ orr r1, #0x7
+ cmp r0, r1
+ beq secondary_startup
+
set_diag_reg
b secondary_startup
ENDPROC(v7_secondary_startup)
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 82e22398d43d..e24a46dc5703 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -11,6 +11,7 @@
#include <asm/proc-fns.h>
#include "common.h"
+#include "hardware.h"
/*
* platform-specific code to shutdown a CPU
@@ -40,5 +41,7 @@ int imx_cpu_kill(unsigned int cpu)
return 0;
imx_enable_cpu(cpu, false);
imx_set_cpu_arg(cpu, 0);
+ if (cpu_is_imx7d())
+ imx_gpcv2_set_core1_pdn_pup_by_software(true);
return 1;
}
diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
index f4da205f57db..a2d35f9ba474 100644
--- a/arch/arm/mach-imx/mach-imx50.c
+++ b/arch/arm/mach-imx/mach-imx50.c
@@ -9,6 +9,12 @@
#include <asm/mach/arch.h>
#include "common.h"
+#include "hardware.h"
+
+static void __init imx50_init_early(void)
+{
+ mxc_set_cpu_type(MXC_CPU_MX50);
+}
static const char * const imx50_dt_board_compat[] __initconst = {
"fsl,imx50",
@@ -16,5 +22,6 @@ static const char * const imx50_dt_board_compat[] __initconst = {
};
DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
+ .init_early = imx50_init_early,
.dt_compat = imx50_dt_board_compat,
MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 703998ebb52e..11dcc369ec14 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -40,27 +40,6 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
return 0;
}
-static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
-{
- phy_write(dev, 0x0d, device);
- phy_write(dev, 0x0e, reg);
- phy_write(dev, 0x0d, (1 << 14) | device);
- phy_write(dev, 0x0e, val);
-}
-
-static int ksz9031rn_phy_fixup(struct phy_device *dev)
-{
- /*
- * min rx data delay, max rx/tx clock delay,
- * min rx/tx control delay
- */
- mmd_write_reg(dev, 2, 4, 0);
- mmd_write_reg(dev, 2, 5, 0);
- mmd_write_reg(dev, 2, 8, 0x003ff);
-
- return 0;
-}
-
/*
* fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
* as they are used for slots1-7 PERST#
@@ -89,75 +68,11 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
-static int ar8031_phy_fixup(struct phy_device *dev)
-{
- u16 val;
-
- /* To enable AR8031 output a 125MHz clk from CLK_25M */
- phy_write(dev, 0xd, 0x7);
- phy_write(dev, 0xe, 0x8016);
- phy_write(dev, 0xd, 0x4007);
-
- val = phy_read(dev, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(dev, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(dev, 0x1d, 0x5);
- val = phy_read(dev, 0x1e);
- val |= 0x0100;
- phy_write(dev, 0x1e, val);
-
- return 0;
-}
-
-#define PHY_ID_AR8031 0x004dd074
-
-static int ar8035_phy_fixup(struct phy_device *dev)
-{
- u16 val;
-
- /* Ar803x phy SmartEEE feature cause link status generates glitch,
- * which cause ethernet link down/up issue, so disable SmartEEE
- */
- phy_write(dev, 0xd, 0x3);
- phy_write(dev, 0xe, 0x805d);
- phy_write(dev, 0xd, 0x4003);
-
- val = phy_read(dev, 0xe);
- phy_write(dev, 0xe, val & ~(1 << 8));
-
- /*
- * Enable 125MHz clock from CLK_25M on the AR8031. This
- * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
- * Also, introduce a tx clock delay.
- *
- * This is the same as is the AR8031 fixup.
- */
- ar8031_phy_fixup(dev);
-
- /*check phy power*/
- val = phy_read(dev, 0x0);
- if (val & BMCR_PDOWN)
- phy_write(dev, 0x0, val & ~BMCR_PDOWN);
-
- return 0;
-}
-
-#define PHY_ID_AR8035 0x004dd072
-
static void __init imx6q_enet_phy_init(void)
{
if (IS_BUILTIN(CONFIG_PHYLIB)) {
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
ksz9021rn_phy_fixup);
- phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
- ksz9031rn_phy_fixup);
- phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef,
- ar8031_phy_fixup);
- phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
- ar8035_phy_fixup);
}
}
@@ -257,9 +172,6 @@ static void __init imx6q_init_machine(void)
imx_get_soc_revision());
imx6q_enet_phy_init();
-
- of_platform_default_populate(NULL, NULL, NULL);
-
imx_anatop_init();
cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
imx6q_1588_init();
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 781e2a94fdd7..e65ed5218f53 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -15,31 +15,6 @@
#include "common.h"
#include "cpuidle.h"
-static int ar8031_phy_fixup(struct phy_device *dev)
-{
- u16 val;
-
- /* Set RGMII IO voltage to 1.8V */
- phy_write(dev, 0x1d, 0x1f);
- phy_write(dev, 0x1e, 0x8);
-
- /* introduce tx clock delay */
- phy_write(dev, 0x1d, 0x5);
- val = phy_read(dev, 0x1e);
- val |= 0x0100;
- phy_write(dev, 0x1e, val);
-
- return 0;
-}
-
-#define PHY_ID_AR8031 0x004dd074
-static void __init imx6sx_enet_phy_init(void)
-{
- if (IS_BUILTIN(CONFIG_PHYLIB))
- phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
- ar8031_phy_fixup);
-}
-
static void __init imx6sx_enet_clk_sel(void)
{
struct regmap *gpr;
@@ -57,7 +32,6 @@ static void __init imx6sx_enet_clk_sel(void)
static inline void imx6sx_enet_init(void)
{
- imx6sx_enet_phy_init();
imx6sx_enet_clk_sel();
}
diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c
index 879c35929a13..6fdd06bcf988 100644
--- a/arch/arm/mach-imx/mach-imx7d.c
+++ b/arch/arm/mach-imx/mach-imx7d.c
@@ -14,25 +14,6 @@
#include "common.h"
-static int ar8031_phy_fixup(struct phy_device *dev)
-{
- u16 val;
-
- /* Set RGMII IO voltage to 1.8V */
- phy_write(dev, 0x1d, 0x1f);
- phy_write(dev, 0x1e, 0x8);
-
- /* disable phy AR8031 SmartEEE function. */
- phy_write(dev, 0xd, 0x3);
- phy_write(dev, 0xe, 0x805d);
- phy_write(dev, 0xd, 0x4003);
- val = phy_read(dev, 0xe);
- val &= ~(0x1 << 8);
- phy_write(dev, 0xe, val);
-
- return 0;
-}
-
static int bcm54220_phy_fixup(struct phy_device *dev)
{
/* enable RXC skew select RGMII copper mode */
@@ -44,14 +25,11 @@ static int bcm54220_phy_fixup(struct phy_device *dev)
return 0;
}
-#define PHY_ID_AR8031 0x004dd074
#define PHY_ID_BCM54220 0x600d8589
static void __init imx7d_enet_phy_init(void)
{
if (IS_BUILTIN(CONFIG_PHYLIB)) {
- phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
- ar8031_phy_fixup);
phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,
bcm54220_phy_fixup);
}
@@ -91,7 +69,7 @@ static void __init imx7d_init_late(void)
static void __init imx7d_init_irq(void)
{
imx_init_revision_from_anatop();
- imx_src_init();
+ imx7_src_init();
irqchip_init();
}
@@ -102,6 +80,7 @@ static const char *const imx7d_dt_compat[] __initconst = {
};
DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)")
+ .smp = smp_ops(imx7_smp_ops),
.init_irq = imx7d_init_irq,
.init_machine = imx7d_init_machine,
.init_late = imx7d_init_late,
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index cf4e9335831c..972639038be5 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -92,6 +92,32 @@ const struct smp_operations imx_smp_ops __initconst = {
#endif
};
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+static void __init imx7_smp_init_cpus(void)
+{
+ struct device_node *np;
+ int i, ncores = 0;
+
+ /* The iMX7D SCU does not report core count, get it from DT */
+ for_each_of_cpu_node(np)
+ ncores++;
+
+ for (i = ncores; i < NR_CPUS; i++)
+ set_cpu_possible(i, false);
+}
+
+const struct smp_operations imx7_smp_ops __initconst = {
+ .smp_init_cpus = imx7_smp_init_cpus,
+ .smp_boot_secondary = imx_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = imx_cpu_die,
+ .cpu_kill = imx_cpu_kill,
+#endif
+};
+
#define DCFG_CCSR_SCRATCHRW1 0x200
static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index f52f371292ac..95fd1fbb0826 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -6,15 +6,19 @@
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/reset-controller.h>
#include <linux/smp.h>
#include <asm/smp_plat.h>
#include "common.h"
+#include "hardware.h"
#define SRC_SCR 0x000
-#define SRC_GPR1 0x020
+#define SRC_GPR1_V1 0x020
+#define SRC_GPR1_V2 0x074
+#define SRC_GPR1(gpr_v2) ((gpr_v2) ? SRC_GPR1_V2 : SRC_GPR1_V1)
#define BP_SRC_SCR_WARM_RESET_ENABLE 0
#define BP_SRC_SCR_SW_GPU_RST 1
#define BP_SRC_SCR_SW_VPU_RST 2
@@ -23,9 +27,18 @@
#define BP_SRC_SCR_SW_IPU2_RST 12
#define BP_SRC_SCR_CORE1_RST 14
#define BP_SRC_SCR_CORE1_ENABLE 22
+/* below is for i.MX7D */
+#define SRC_A7RCR1 0x008
+#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
+#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
+#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
+#define GPC_PGC_C1 0x840
+#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
static void __iomem *src_base;
static DEFINE_SPINLOCK(scr_lock);
+static bool gpr_v2;
+static void __iomem *gpc_base;
static const int sw_reset_bits[5] = {
BP_SRC_SCR_SW_GPU_RST,
@@ -73,17 +86,64 @@ static struct reset_controller_dev imx_reset_controller = {
.nr_resets = ARRAY_SIZE(sw_reset_bits),
};
+static void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
+{
+ writel_relaxed(enable, gpc_base + offset);
+}
+
+/*
+ * The motivation for bringing up the second i.MX7D core inside the kernel
+ * is that legacy vendor bootloaders usually do not implement PSCI support.
+ * This is a significant blocker for systems in the field that are running old
+ * bootloader versions to upgrade to a modern mainline kernel version, as only
+ * one CPU of the i.MX7D would be brought up.
+ * Bring up the second i.MX7D core inside the kernel to make the migration
+ * path to mainline kernel easier for the existing iMX7D users.
+ */
+void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn)
+{
+ u32 reg = pdn ? GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ;
+ u32 val, pup;
+ int ret;
+
+ imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
+ val = readl_relaxed(gpc_base + reg);
+ val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
+ writel_relaxed(val, gpc_base + reg);
+
+ ret = readl_relaxed_poll_timeout_atomic(gpc_base + reg, pup,
+ !(pup & BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7),
+ 5, 1000000);
+ if (ret < 0) {
+ pr_err("i.MX7D: CORE1_A7 power up timeout\n");
+ val &= ~BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
+ writel_relaxed(val, gpc_base + reg);
+ }
+
+ imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
+}
+
void imx_enable_cpu(int cpu, bool enable)
{
u32 mask, val;
cpu = cpu_logical_map(cpu);
- mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
spin_lock(&scr_lock);
- val = readl_relaxed(src_base + SRC_SCR);
- val = enable ? val | mask : val & ~mask;
- val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
- writel_relaxed(val, src_base + SRC_SCR);
+ if (gpr_v2) {
+ if (enable)
+ imx_gpcv2_set_core1_pdn_pup_by_software(false);
+
+ mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
+ val = readl_relaxed(src_base + SRC_A7RCR1);
+ val = enable ? val | mask : val & ~mask;
+ writel_relaxed(val, src_base + SRC_A7RCR1);
+ } else {
+ mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
+ val = readl_relaxed(src_base + SRC_SCR);
+ val = enable ? val | mask : val & ~mask;
+ val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
+ writel_relaxed(val, src_base + SRC_SCR);
+ }
spin_unlock(&scr_lock);
}
@@ -91,19 +151,19 @@ void imx_set_cpu_jump(int cpu, void *jump_addr)
{
cpu = cpu_logical_map(cpu);
writel_relaxed(__pa_symbol(jump_addr),
- src_base + SRC_GPR1 + cpu * 8);
+ src_base + SRC_GPR1(gpr_v2) + cpu * 8);
}
u32 imx_get_cpu_arg(int cpu)
{
cpu = cpu_logical_map(cpu);
- return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
+ return readl_relaxed(src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4);
}
void imx_set_cpu_arg(int cpu, u32 arg)
{
cpu = cpu_logical_map(cpu);
- writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
+ writel_relaxed(arg, src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4);
}
void __init imx_src_init(void)
@@ -131,3 +191,26 @@ void __init imx_src_init(void)
writel_relaxed(val, src_base + SRC_SCR);
spin_unlock(&scr_lock);
}
+
+void __init imx7_src_init(void)
+{
+ struct device_node *np;
+
+ gpr_v2 = true;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-src");
+ if (!np)
+ return;
+
+ src_base = of_iomap(np, 0);
+ if (!src_base)
+ return;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpc");
+ if (!np)
+ return;
+
+ gpc_base = of_iomap(np, 0);
+ if (!gpc_base)
+ return;
+}
diff --git a/arch/arm/mach-imx/suspend-imx53.S b/arch/arm/mach-imx/suspend-imx53.S
index 41b8aad65363..46570ec2fbcf 100644
--- a/arch/arm/mach-imx/suspend-imx53.S
+++ b/arch/arm/mach-imx/suspend-imx53.S
@@ -28,11 +28,11 @@
* ^
* ^
* imx53_suspend code
- * PM_INFO structure(imx53_suspend_info)
+ * PM_INFO structure(imx5_cpu_suspend_info)
* ======================== low address =======================
*/
-/* Offsets of members of struct imx53_suspend_info */
+/* Offsets of members of struct imx5_cpu_suspend_info */
#define SUSPEND_INFO_MX53_M4IF_V_OFFSET 0x0
#define SUSPEND_INFO_MX53_IOMUXC_V_OFFSET 0x4
#define SUSPEND_INFO_MX53_IO_COUNT_OFFSET 0x8
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 165c184801e1..bf14d65120b9 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -7,7 +7,7 @@ comment "IXP4xx Platforms"
config MACH_IXP4XX_OF
bool
- prompt "Devce Tree IXP4xx boards"
+ prompt "Device Tree IXP4xx boards"
default y
select ARM_APPENDED_DTB # Old Redboot bootloaders deployed
select I2C
@@ -20,7 +20,7 @@ config MACH_IXP4XX_OF
config MACH_NSLU2
bool
prompt "Linksys NSLU2"
- select FORCE_PCI
+ depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Linksys's
NSLU2 NAS device. For more information on this platform,
@@ -28,7 +28,7 @@ config MACH_NSLU2
config MACH_AVILA
bool "Avila"
- select FORCE_PCI
+ depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support the Gateworks
Avila Network Platform. For more information on this platform,
@@ -44,7 +44,7 @@ config MACH_LOFT
config ARCH_ADI_COYOTE
bool "Coyote"
- select FORCE_PCI
+ depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support the ADI
Engineering Coyote Gateway Reference Platform. For more
@@ -52,7 +52,7 @@ config ARCH_ADI_COYOTE
config MACH_GATEWAY7001
bool "Gateway 7001"
- select FORCE_PCI
+ depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Gateway's
7001 Access Point. For more information on this platform,
@@ -60,7 +60,7 @@ config MACH_GATEWAY7001
config MACH_WG302V2
bool "Netgear WG302 v2 / WAG302 v2"
- select FORCE_PCI
+ depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Netgear's
WG302 v2 or WAG302 v2 Access Points. For more information
@@ -68,6 +68,7 @@ config MACH_WG302V2
config ARCH_IXDP425
bool "IXDP425"
+ depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Intel's
IXDP425 Development Platform (Also known as Richfield).
@@ -75,6 +76,7 @@ config ARCH_IXDP425
config MACH_IXDPG425
bool "IXDPG425"
+ depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Intel's
IXDPG425 Development Platform (Also known as Montajade).
@@ -120,7 +122,7 @@ config ARCH_PRPMC1100
config MACH_NAS100D
bool
prompt "NAS100D"
- select FORCE_PCI
+ depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Iomega's
NAS 100d device. For more information on this platform,
@@ -129,7 +131,7 @@ config MACH_NAS100D
config MACH_DSMG600
bool
prompt "D-Link DSM-G600 RevA"
- select FORCE_PCI
+ depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support D-Link's
DSM-G600 RevA device. For more information on this platform,
@@ -143,7 +145,7 @@ config ARCH_IXDP4XX
config MACH_FSG
bool
prompt "Freecom FSG-3"
- select FORCE_PCI
+ depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Freecom's
FSG-3 device. For more information on this platform,
@@ -152,7 +154,7 @@ config MACH_FSG
config MACH_ARCOM_VULCAN
bool
prompt "Arcom/Eurotech Vulcan"
- select FORCE_PCI
+ depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support Arcom's
Vulcan board.
@@ -173,7 +175,7 @@ config CPU_IXP43X
config MACH_GTWX5715
bool "Gemtek WX5715 (Linksys WRV54G)"
depends on ARCH_IXP4XX
- select FORCE_PCI
+ depends on IXP4XX_PCI_LEGACY
help
This board is currently inside the Linksys WRV54G Gateways.
@@ -196,7 +198,7 @@ config MACH_DEVIXP
config MACH_MICCPT
bool "Omicron MICCPT"
- select FORCE_PCI
+ depends on IXP4XX_PCI_LEGACY
help
Say 'Y' here if you want your kernel to support the MICCPT
board from OMICRON electronics GmbH.
@@ -209,9 +211,16 @@ config MACH_MIC256
comment "IXP4xx Options"
+config IXP4XX_PCI_LEGACY
+ bool "IXP4xx legacy PCI driver support"
+ depends on PCI
+ help
+ Selects legacy PCI driver.
+ Not recommended for new development.
+
config IXP4XX_INDIRECT_PCI
bool "Use indirect PCI memory access"
- depends on PCI
+ depends on IXP4XX_PCI_LEGACY
help
IXP4xx provides two methods of accessing PCI memory space:
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index 1981b33109cb..ec1d3029f80c 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -19,6 +19,7 @@
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/gpio/machine.h>
+#include <linux/platform_data/pata_ixp4xx_cf.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 007a44412e24..b5eadd70d903 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -27,12 +27,12 @@
#include <linux/cpu.h>
#include <linux/pci.h>
#include <linux/sched_clock.h>
+#include <linux/soc/ixp4xx/cpu.h>
#include <linux/irqchip/irq-ixp4xx.h>
#include <linux/platform_data/timer-ixp4xx.h>
#include <linux/dma-map-ops.h>
#include <mach/udc.h>
#include <mach/hardware.h>
-#include <mach/io.h>
#include <linux/uaccess.h>
#include <asm/page.h>
#include <asm/exception.h>
@@ -44,6 +44,27 @@
#include "irqs.h"
+u32 ixp4xx_read_feature_bits(void)
+{
+ u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
+
+ if (cpu_is_ixp42x_rev_a0())
+ return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
+ IXP4XX_FEATURE_AES);
+ if (cpu_is_ixp42x())
+ return val & IXP42X_FEATURE_MASK;
+ if (cpu_is_ixp43x())
+ return val & IXP43X_FEATURE_MASK;
+ return val & IXP46X_FEATURE_MASK;
+}
+EXPORT_SYMBOL(ixp4xx_read_feature_bits);
+
+void ixp4xx_write_feature_bits(u32 value)
+{
+ __raw_writel(~value, IXP4XX_EXP_CFG2);
+}
+EXPORT_SYMBOL(ixp4xx_write_feature_bits);
+
#define IXP4XX_TIMER_FREQ 66666000
/*************************************************************************
@@ -215,6 +236,27 @@ static struct resource ixp46x_i2c_resources[] = {
}
};
+/* A single 32-bit register on IXP46x */
+#define IXP4XX_HWRANDOM_BASE_PHYS 0x70002100
+
+static struct resource ixp46x_hwrandom_resource[] = {
+ {
+ .start = IXP4XX_HWRANDOM_BASE_PHYS,
+ .end = IXP4XX_HWRANDOM_BASE_PHYS + 0x3,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device ixp46x_hwrandom_device = {
+ .name = "ixp4xx-hwrandom",
+ .id = -1,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = ixp46x_hwrandom_resource,
+ .num_resources = ARRAY_SIZE(ixp46x_hwrandom_resource),
+};
+
/*
* I2C controller. The IXP46x uses the same block as the IOP3xx, so
* we just use the same device name.
@@ -227,7 +269,8 @@ static struct platform_device ixp46x_i2c_controller = {
};
static struct platform_device *ixp46x_devices[] __initdata = {
- &ixp46x_i2c_controller
+ &ixp46x_hwrandom_device,
+ &ixp46x_i2c_controller,
};
unsigned long ixp4xx_exp_bus_size;
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 507ee3878769..844329c5610d 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -28,6 +28,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
+#include <mach/hardware.h>
#include "irqs.h"
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
deleted file mode 100644
index b872a5354ddd..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/cpu.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-ixp4xx/include/mach/cpu.h
- *
- * IXP4XX cpu type detection
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- */
-
-#ifndef __ASM_ARCH_CPU_H__
-#define __ASM_ARCH_CPU_H__
-
-#include <linux/io.h>
-#include <asm/cputype.h>
-
-/* Processor id value in CP15 Register 0 */
-#define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */
-#define IXP42X_PROCESSOR_ID_MASK 0xffffffc0
-
-#define IXP43X_PROCESSOR_ID_VALUE 0x69054040
-#define IXP43X_PROCESSOR_ID_MASK 0xfffffff0
-
-#define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */
-#define IXP46X_PROCESSOR_ID_MASK 0xfffffff0
-
-#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
- IXP42X_PROCESSOR_ID_VALUE)
-#define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
- IXP42X_PROCESSOR_ID_VALUE)
-#define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
- IXP43X_PROCESSOR_ID_VALUE)
-#define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
- IXP46X_PROCESSOR_ID_VALUE)
-
-static inline u32 ixp4xx_read_feature_bits(void)
-{
- u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
-
- if (cpu_is_ixp42x_rev_a0())
- return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
- IXP4XX_FEATURE_AES);
- if (cpu_is_ixp42x())
- return val & IXP42X_FEATURE_MASK;
- if (cpu_is_ixp43x())
- return val & IXP43X_FEATURE_MASK;
- return val & IXP46X_FEATURE_MASK;
-}
-
-static inline void ixp4xx_write_feature_bits(u32 value)
-{
- __raw_writel(~value, IXP4XX_EXP_CFG2);
-}
-
-#endif /* _ASM_ARCH_CPU_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
index b884eedcd0fc..b2b7301ce503 100644
--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -23,7 +23,7 @@
#include "ixp4xx-regs.h"
#ifndef __ASSEMBLER__
-#include <mach/cpu.h>
+#include <linux/soc/ixp4xx/cpu.h>
#endif
/* Platform helper functions and definitions */
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
index 708d085ce39f..abb07f105515 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -45,21 +45,21 @@
* it can be used with the low-level debug code.
*/
#define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000
-#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEC00000)
#define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000
/*
* PCI Config registers
*/
#define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000
-#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000)
+#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEC13000)
#define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000
/*
* Expansion BUS Configuration registers
*/
#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
-#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000
+#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000
#define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000
#define IXP4XX_EXP_CS0_OFFSET 0x00
@@ -120,6 +120,7 @@
#define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
+/* The UART is explicitly put in the beginning of fixmap */
#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
@@ -299,58 +300,4 @@
#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
-/* "fuse" bits of IXP_EXP_CFG2 */
-/* All IXP4xx CPUs */
-#define IXP4XX_FEATURE_RCOMP (1 << 0)
-#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
-#define IXP4XX_FEATURE_HASH (1 << 2)
-#define IXP4XX_FEATURE_AES (1 << 3)
-#define IXP4XX_FEATURE_DES (1 << 4)
-#define IXP4XX_FEATURE_HDLC (1 << 5)
-#define IXP4XX_FEATURE_AAL (1 << 6)
-#define IXP4XX_FEATURE_HSS (1 << 7)
-#define IXP4XX_FEATURE_UTOPIA (1 << 8)
-#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
-#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
-#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
-#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
-#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
-#define IXP4XX_FEATURE_PCI (1 << 14)
-#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
-#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
-#define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \
- IXP4XX_FEATURE_USB_DEVICE | \
- IXP4XX_FEATURE_HASH | \
- IXP4XX_FEATURE_AES | \
- IXP4XX_FEATURE_DES | \
- IXP4XX_FEATURE_HDLC | \
- IXP4XX_FEATURE_AAL | \
- IXP4XX_FEATURE_HSS | \
- IXP4XX_FEATURE_UTOPIA | \
- IXP4XX_FEATURE_NPEB_ETH0 | \
- IXP4XX_FEATURE_NPEC_ETH | \
- IXP4XX_FEATURE_RESET_NPEA | \
- IXP4XX_FEATURE_RESET_NPEB | \
- IXP4XX_FEATURE_RESET_NPEC | \
- IXP4XX_FEATURE_PCI | \
- IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
- IXP4XX_FEATURE_XSCALE_MAX_FREQ)
-
-
-/* IXP43x/46x CPUs */
-#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
-#define IXP4XX_FEATURE_USB_HOST (1 << 18)
-#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
-#define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \
- IXP4XX_FEATURE_ECC_TIMESYNC | \
- IXP4XX_FEATURE_USB_HOST | \
- IXP4XX_FEATURE_NPEA_ETH)
-
-/* IXP46x CPU (including IXP455) only */
-#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
-#define IXP4XX_FEATURE_RSA (1 << 21)
-#define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \
- IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
- IXP4XX_FEATURE_RSA)
-
#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index 6d403fe0bf52..d8b4df96db08 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -80,20 +80,6 @@ extern unsigned long ixp4xx_exp_bus_size;
#define IXP4XX_UART_XTAL 14745600
/*
- * This structure provide a means for the board setup code
- * to give information to th pata_ixp4xx driver. It is
- * passed as platform_data.
- */
-struct ixp4xx_pata_data {
- volatile u32 *cs0_cfg;
- volatile u32 *cs1_cfg;
- unsigned long cs0_bits;
- unsigned long cs1_bits;
- void __iomem *cs0;
- void __iomem *cs1;
-};
-
-/*
* Frequency of clock used for primary clocksource
*/
extern unsigned long ixp4xx_timer_freq;
diff --git a/arch/arm/mach-ixp4xx/ixp4xx-of.c b/arch/arm/mach-ixp4xx/ixp4xx-of.c
index 7449b8319c8a..f9904716ec7f 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx-of.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx-of.c
@@ -9,8 +9,12 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include <mach/ixp4xx-regs.h>
+/*
+ * These are the only fixed phys to virt mappings we ever need
+ * we put it right after the UART mapping at 0xffc80000-0xffc81fff
+ */
+#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
+#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000
static struct map_desc ixp4xx_of_io_desc[] __initdata = {
/*
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index 6959ad2e3aec..6133cf01cbe4 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -33,6 +33,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
+#include <mach/hardware.h>
#include "irqs.h"
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index a428bb918703..8526a70e401b 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -31,6 +31,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/time.h>
+#include <mach/hardware.h>
#include "irqs.h"
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 9536b8f3c07d..208c700c2455 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -65,14 +65,14 @@ config MACH_OMAP_INNOVATOR
config MACH_OMAP_H2
bool "TI H2 Support"
depends on ARCH_OMAP16XX
- help
+ help
TI OMAP 1610/1611B H2 board support. Say Y here if you have such
a board.
config MACH_OMAP_H3
bool "TI H3 Support"
depends on ARCH_OMAP16XX
- help
+ help
TI OMAP 1710 H3 board support. Say Y here if you have such
a board.
@@ -85,14 +85,14 @@ config MACH_HERALD
config MACH_OMAP_OSK
bool "TI OSK Support"
depends on ARCH_OMAP16XX
- help
+ help
TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here
if you have such a board.
config OMAP_OSK_MISTRAL
bool "Mistral QVGA board Support"
depends on MACH_OMAP_OSK
- help
+ help
The OSK supports an optional add-on board with a Quarter-VGA
touchscreen, PDA-ish buttons, a resume button, bicolor LED,
and camera connector. Say Y here if you have this board.
@@ -100,14 +100,14 @@ config OMAP_OSK_MISTRAL
config MACH_OMAP_PERSEUS2
bool "TI Perseus2"
depends on ARCH_OMAP730
- help
+ help
Support for TI OMAP 730 Perseus2 board. Say Y here if you have such
a board.
config MACH_OMAP_FSAMPLE
bool "TI F-Sample"
depends on ARCH_OMAP730
- help
+ help
Support for TI OMAP 850 F-Sample board. Say Y here if you have such
a board.
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index d02fe63dab59..14beb59e5f7b 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -26,7 +26,6 @@
extern struct omap_domain_base cm_base;
extern struct omap_domain_base cm2_base;
-extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
# endif
/*
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index b7ea609386d5..e2d069fe67f1 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -38,19 +38,6 @@ struct omap_domain_base cm2_base;
#define CM_SINGLE_INSTANCE 0x2
/**
- * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
- * @cm: CM base virtual address
- * @cm2: CM2 base virtual address (if present on the booted SoC)
- *
- * XXX Will be replaced when the PRM/CM drivers are completed.
- */
-void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2)
-{
- cm_base.va = cm;
- cm2_base.va = cm2;
-}
-
-/**
* cm_split_idlest_reg - split CM_IDLEST reg addr into its components
* @idlest_reg: CM_IDLEST* virtual address
* @prcm_inst: pointer to an s16 to return the PRCM instance offset
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index db446f271f5d..32f58f58515e 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -130,7 +130,6 @@ void am33xx_init_early(void);
void am35xx_init_early(void);
void ti814x_init_early(void);
void ti816x_init_early(void);
-void am33xx_init_early(void);
void am43xx_init_early(void);
void am43xx_init_late(void);
void omap4430_init_early(void);
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 73338cf80d76..062d431fc33a 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -136,11 +136,6 @@ struct omap3_control_regs {
static struct omap3_control_regs control_context;
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
-void __init omap2_set_globals_control(void __iomem *ctrl)
-{
- omap2_ctrl_base = ctrl;
-}
-
u8 omap_ctrl_readb(u16 offset)
{
u32 val;
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index eceb4b09adb2..c4ca30ba1790 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -528,7 +528,6 @@ extern int omap3_ctrl_save_padconf(void);
void omap3_ctrl_init(void);
int omap2_control_base_init(void);
int omap_control_init(void);
-void omap2_set_globals_control(void __iomem *ctrl);
void __init omap3_control_legacy_iomap_init(void);
#else
#define omap_ctrl_readb(x) 0
diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c
index 56f2c0bcae5a..bf0d25fd2cea 100644
--- a/arch/arm/mach-omap2/pm33xx-core.c
+++ b/arch/arm/mach-omap2/pm33xx-core.c
@@ -8,6 +8,7 @@
#include <linux/cpuidle.h>
#include <linux/platform_data/pm33xx.h>
+#include <linux/suspend.h>
#include <asm/cpuidle.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>
@@ -324,6 +325,44 @@ static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void)
return NULL;
}
+#ifdef CONFIG_SUSPEND
+/*
+ * Block system suspend initially. Later on pm33xx sets up it's own
+ * platform_suspend_ops after probe. That depends also on loaded
+ * wkup_m3_ipc and booted am335x-pm-firmware.elf.
+ */
+static int amx3_suspend_block(suspend_state_t state)
+{
+ pr_warn("PM not initialized for pm33xx, wkup_m3_ipc, or am335x-pm-firmware.elf\n");
+
+ return -EINVAL;
+}
+
+static int amx3_pm_valid(suspend_state_t state)
+{
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+static const struct platform_suspend_ops amx3_blocked_pm_ops = {
+ .begin = amx3_suspend_block,
+ .valid = amx3_pm_valid,
+};
+
+static void __init amx3_block_suspend(void)
+{
+ suspend_set_ops(&amx3_blocked_pm_ops);
+}
+#else
+static inline void amx3_block_suspend(void)
+{
+}
+#endif /* CONFIG_SUSPEND */
+
int __init amx3_common_pm_init(void)
{
struct am33xx_pm_platform_data *pdata;
@@ -337,6 +376,7 @@ int __init amx3_common_pm_init(void)
devinfo.size_data = sizeof(*pdata);
devinfo.id = -1;
platform_device_register_full(&devinfo);
+ amx3_block_suspend();
return 0;
}
diff --git a/arch/arm/mach-s3c/mach-rx1950.c b/arch/arm/mach-s3c/mach-rx1950.c
index a3f46aa61c45..313e080e179e 100644
--- a/arch/arm/mach-s3c/mach-rx1950.c
+++ b/arch/arm/mach-s3c/mach-rx1950.c
@@ -271,7 +271,6 @@ static int rx1950_led_blink_set(struct gpio_desc *desc, int state,
break;
default:
return -EINVAL;
- break;
}
if (delay_on && delay_off && !*delay_on && !*delay_off)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 7336c1fd0dda..b0ce18d4cc98 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -16,6 +16,7 @@ config ARCH_SUNXI
select IRQ_FASTEOI_HIERARCHY_HANDLERS
select PINCTRL
select RESET_CONTROLLER
+ select SUN4I_TIMER
help
This enables support for Allwinner sunxi based SoCs like the A64.
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index e22b94c83647..5e66ce1a334f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -79,7 +79,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii-txid";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <&reg_dc1sw>;
status = "okay";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 634a91af8e83..4b854eb21f72 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -227,7 +227,7 @@
<&pcie_phy 2>, <&pcie_phy 3>;
phy-names = "pcie-phy-0", "pcie-phy-1",
"pcie-phy-2", "pcie-phy-3";
- ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
+ ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
<0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,