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authorTushar Behera <tushar.b@samsung.com>2014-07-08 03:31:41 +0400
committerKukjin Kim <kgene.kim@samsung.com>2014-07-08 03:31:41 +0400
commitbe0b420ad6123e587738a67a9eff3ec213a57604 (patch)
treecfd40f05975ad63412e3836d91e3193ac2f4b6fb /arch
parentcd3de83f147601356395b57a8673e9c5ff1e59d1 (diff)
downloadlinux-be0b420ad6123e587738a67a9eff3ec213a57604.tar.xz
ARM: dts: Update the parent for Audss clocks in Exynos5420
Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux. As per the user manual, it should be CLK_MAU_EPLL. The problem surfaced when the bootloader in Peach-pit board set the EPLL clock as the parent of AUDSS mux. While booting the kernel, we used to get a system hang during late boot if CLK_MAU_EPLL was disabled. Signed-off-by: Tushar Behera <tushar.b@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Reported-by: Kevin Hilman <khilman@linaro.org> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e38532271ef9..79e9119d3f8d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -167,7 +167,7 @@
compatible = "samsung,exynos5420-audss-clock";
reg = <0x03810000 0x0C>;
#clock-cells = <1>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};