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| author | Pierre Gondois <pierre.gondois@arm.com> | 2022-11-07 18:57:05 +0300 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2022-11-08 14:34:23 +0300 |
| commit | ce459b1da752cf1dc0b81aba999a6542ab866993 (patch) | |
| tree | c46abdc9b52acb600ec75b028677f7e3e6d3259c /arch | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff) | |
| download | linux-ce459b1da752cf1dc0b81aba999a6542ab866993.tar.xz | |
arm64: dts: Update cache properties for mediatek
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-13-pierre.gondois@arm.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 |
3 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 64693c17af9e..c326aeb33a10 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -198,16 +198,19 @@ l2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 6b20376191a7..424fc89cc6f7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -169,16 +169,19 @@ l2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; idle-states { diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 905d1a90b406..cb74905cfbb8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -213,16 +213,19 @@ l2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; |