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authorLinus Torvalds <torvalds@linux-foundation.org>2022-03-25 23:35:34 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2022-03-25 23:35:34 +0300
commite35a4a4e13c35f500a8d38e836b5e335c7515494 (patch)
tree32940f68475c16ddee8ed2933c9a4ae6e9b44265 /drivers/bcma
parent8eb48fc7c54ed627a693a205570f0eceea64274c (diff)
parent6cadd424abb63120f8346a4509dc43bddc9401d3 (diff)
downloadlinux-e35a4a4e13c35f500a8d38e836b5e335c7515494.tar.xz
Merge tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Miquel Raynal: "There has been a lot of activity in the MTD subsystem recently, with a number of SPI-NOR cleanups as well as the introduction of ECC engines that can be used by SPI controllers (hence a few SPI patches in here). Core MTD changes: - Replace the expert mode symbols with a single helper - Fix misuses of of_match_ptr() - Remove partid and partname debugfs files - tests: Fix eraseblock read speed miscalculation for lower partition sizes - TRX parser: Allow to use on MediaTek MIPS SoCs MTD driver changes: - spear_smi: use GFP_KERNEL - mchp48l640: Add SPI ID table - mchp23k256: Add SPI ID table - blkdevs: Avoid soft lockups with some mtd/spi devices - aspeed-smc: Improve probe resilience Hyperbus changes: - HBMC_AM654 should depend on ARCH_K3 NAND core changes: - ECC: - Add infrastructure to support hardware engines - Add a new helper to retrieve the ECC context - Provide a helper to retrieve a pilelined engine device NAND-ECC changes: - Macronix ECC engine: - Add Macronix external ECC engine support - Support SPI pipelined mode - Make two read-only arrays static const - Fix compile test issue Raw NAND core changes: - Fix misuses of of_match_node() - Rework of_get_nand_bus_width() - Remove of_get_nand_on_flash_bbt() wrapper - Protect access to rawnand devices while in suspend - bindings: Document the wp-gpios property Rax NAND controller driver changes: - atmel: Fix refcount issue in atmel_nand_controller_init - nandsim: - Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern - Merge repeat codes in ns_switch_state - Replace overflow check with kzalloc to single kcalloc - rockchip: Fix platform_get_irq.cocci warning - stm32_fmc2: Add NAND Write Protect support - pl353: Set the nand chip node as the flash node - brcmnand: Fix sparse warnings in bcma_nand - omap_elm: Remove redundant variable 'errors' - gpmi: - Support fast edo timings for mx28 - Validate controller clock rate - Fix controller timings setting - brcmnand: - Add BCMA shim - BCMA controller uses command shift of 0 - Allow platform data instantation - Add platform data structure for BCMA - Allow working without interrupts - Move OF operations out of brcmnand_init_cs() - Avoid pdev in brcmnand_init_cs() - Allow SoC to provide I/O operations - Assign soc as early as possible Onenand changes: - Check for error irq SPI-NAND core changes: - Delay a little bit the dirmap creation - Create direct mapping descriptors for ECC operations SPI-NAND driver changes: - macronix: Use random program load SPI NOR core changes: - Move vendor specific code out of the core into vendor drivers. - Unify all function and object names in the vendor modules. - Make setup() callback optional to improve readability. - Skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash declaration. SPI changes: - Macronix SPI controller: - Fix the transmit path - Create a helper to configure the controller before an operation - Create a helper to ease the start of an operation - Add support for direct mapping - Add support for pipelined ECC operations - spi-mem: - Introduce a capability structure - Check the controller extra capabilities - cadence-quadspi/mxic: Provide capability structures - Kill the spi_mem_dtr_supports_op() helper - Add an ecc parameter to the spi_mem_op structure Binding changes: - Dropped mtd/cortina,gemini-flash.txt - Convert BCM47xx partitions to json-schema - Vendor prefixes: Clarify Macronix prefix - SPI NAND: Convert spi-nand description file to yaml - Raw NAND chip: Create a NAND chip description - Raw NAND controller: - Harmonize the property types - Fix a comment in the examples - Fix the reg property description - Describe Macronix NAND ECC engine - Macronix SPI controller: - Document the nand-ecc-engine property - Convert to yaml - The interrupt property is not mandatory" * tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (104 commits) mtd: nand: ecc: mxic: Fix compile test issue mtd: nand: mxic-ecc: make two read-only arrays static const mtd: hyperbus: HBMC_AM654 should depend on ARCH_K3 mtd: core: Remove partid and partname debugfs files dt-bindings: mtd: partitions: convert BCM47xx to the json-schema mtd: tests: Fix eraseblock read speed miscalculation for lower partition sizes mtd: rawnand: atmel: fix refcount issue in atmel_nand_controller_init mtd: rawnand: rockchip: fix platform_get_irq.cocci warning mtd: spi-nor: Skip erase logic when SPI_NOR_NO_ERASE is set mtd: spi-nor: renumber flags mtd: spi-nor: slightly change code style in spi_nor_sr_ready() mtd: spi-nor: spansion: rename vendor specific functions and defines mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag mtd: spi-nor: move all spansion specifics into spansion.c mtd: spi-nor: spansion: slightly rework control flow in late_init() mtd: spi-nor: micron-st: rename vendor specific functions and defines mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag mtd: spi-nor: move all micron-st specifics into micron-st.c mtd: spi-nor: xilinx: correct the debug message mtd: spi-nor: xilinx: rename vendor specific functions and defines ...
Diffstat (limited to 'drivers/bcma')
-rw-r--r--drivers/bcma/driver_chipcommon_nflash.c20
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/bcma/driver_chipcommon_nflash.c b/drivers/bcma/driver_chipcommon_nflash.c
index d4f699aef8c4..a1a814750b4a 100644
--- a/drivers/bcma/driver_chipcommon_nflash.c
+++ b/drivers/bcma/driver_chipcommon_nflash.c
@@ -7,18 +7,28 @@
#include "bcma_private.h"
+#include <linux/bitops.h>
#include <linux/platform_device.h>
+#include <linux/platform_data/brcmnand.h>
#include <linux/bcma/bcma.h>
+/* Alternate NAND controller driver name in order to allow both bcm47xxnflash
+ * and bcma_brcmnand to be built into the same kernel image.
+ */
+static const char *bcma_nflash_alt_name = "bcma_brcmnand";
+
struct platform_device bcma_nflash_dev = {
.name = "bcma_nflash",
.num_resources = 0,
};
+static const char *probes[] = { "bcm47xxpart", NULL };
+
/* Initialize NAND flash access */
int bcma_nflash_init(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
+ u32 reg;
if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
cc->core->id.rev != 38) {
@@ -33,8 +43,16 @@ int bcma_nflash_init(struct bcma_drv_cc *cc)
cc->nflash.present = true;
if (cc->core->id.rev == 38 &&
- (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
+ (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)) {
cc->nflash.boot = true;
+ /* Determine the chip select that is being used */
+ reg = bcma_cc_read32(cc, BCMA_CC_NAND_CS_NAND_SELECT) & 0xff;
+ cc->nflash.brcmnand_info.chip_select = ffs(reg) - 1;
+ cc->nflash.brcmnand_info.part_probe_types = probes;
+ cc->nflash.brcmnand_info.ecc_stepsize = 512;
+ cc->nflash.brcmnand_info.ecc_strength = 1;
+ bcma_nflash_dev.name = bcma_nflash_alt_name;
+ }
/* Prepare platform device, but don't register it yet. It's too early,
* malloc (required by device_private_init) is not available yet. */