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authorKevin Gan <ganhy@marvell.com>2011-04-09 05:19:33 +0400
committerGustavo F. Padovan <padovan@profusion.mobi>2011-04-13 19:20:05 +0400
commit9f72c1d977e47a7d182d49ea131067cba0a96ab8 (patch)
tree2f0f2627c3cad459994639617bd55e050fd1d17a /drivers/bluetooth/btmrvl_sdio.h
parentb86ed368f1f0b19de1918c57e4b056e73d5613a0 (diff)
downloadlinux-9f72c1d977e47a7d182d49ea131067cba0a96ab8.tar.xz
Bluetooth: btmrvl: support Marvell Bluetooth device SD8787
The SD8787 firmware image is shared with mwifiex driver. Whoever gets loaded first will be responsible for firmware downloading. Signed-off-by: Kevin Gan <ganhy@marvell.com> Signed-off-by: Tristan Xu <xurf@marvell.com> Signed-off-by: Bing Zhao <bzhao@marvell.com> Signed-off-by: Gustavo F. Padovan <padovan@profusion.mobi>
Diffstat (limited to 'drivers/bluetooth/btmrvl_sdio.h')
-rw-r--r--drivers/bluetooth/btmrvl_sdio.h68
1 files changed, 36 insertions, 32 deletions
diff --git a/drivers/bluetooth/btmrvl_sdio.h b/drivers/bluetooth/btmrvl_sdio.h
index 27329f107e5a..43d35a609ca9 100644
--- a/drivers/bluetooth/btmrvl_sdio.h
+++ b/drivers/bluetooth/btmrvl_sdio.h
@@ -47,44 +47,46 @@
/* Max retry number of CMD53 write */
#define MAX_WRITE_IOMEM_RETRY 2
-/* Host Control Registers */
-#define IO_PORT_0_REG 0x00
-#define IO_PORT_1_REG 0x01
-#define IO_PORT_2_REG 0x02
-
-#define CONFIG_REG 0x03
-#define HOST_POWER_UP BIT(1)
-#define HOST_CMD53_FIN BIT(2)
-
-#define HOST_INT_MASK_REG 0x04
-#define HIM_DISABLE 0xff
-#define HIM_ENABLE (BIT(0) | BIT(1))
-
-#define HOST_INTSTATUS_REG 0x05
-#define UP_LD_HOST_INT_STATUS BIT(0)
-#define DN_LD_HOST_INT_STATUS BIT(1)
-
-/* Card Control Registers */
-#define SQ_READ_BASE_ADDRESS_A0_REG 0x10
-#define SQ_READ_BASE_ADDRESS_A1_REG 0x11
-
-#define CARD_STATUS_REG 0x20
-#define DN_LD_CARD_RDY BIT(0)
-#define CARD_IO_READY BIT(3)
-
-#define CARD_FW_STATUS0_REG 0x40
-#define CARD_FW_STATUS1_REG 0x41
-#define FIRMWARE_READY 0xfedc
-
-#define CARD_RX_LEN_REG 0x42
-#define CARD_RX_UNIT_REG 0x43
-
+/* register bitmasks */
+#define HOST_POWER_UP BIT(1)
+#define HOST_CMD53_FIN BIT(2)
+
+#define HIM_DISABLE 0xff
+#define HIM_ENABLE (BIT(0) | BIT(1))
+
+#define UP_LD_HOST_INT_STATUS BIT(0)
+#define DN_LD_HOST_INT_STATUS BIT(1)
+
+#define DN_LD_CARD_RDY BIT(0)
+#define CARD_IO_READY BIT(3)
+
+#define FIRMWARE_READY 0xfedc
+
+
+struct btmrvl_sdio_card_reg {
+ u8 cfg;
+ u8 host_int_mask;
+ u8 host_intstatus;
+ u8 card_status;
+ u8 sq_read_base_addr_a0;
+ u8 sq_read_base_addr_a1;
+ u8 card_revision;
+ u8 card_fw_status0;
+ u8 card_fw_status1;
+ u8 card_rx_len;
+ u8 card_rx_unit;
+ u8 io_port_0;
+ u8 io_port_1;
+ u8 io_port_2;
+};
struct btmrvl_sdio_card {
struct sdio_func *func;
u32 ioport;
const char *helper;
const char *firmware;
+ const struct btmrvl_sdio_card_reg *reg;
+ u16 sd_blksz_fw_dl;
u8 rx_unit;
struct btmrvl_private *priv;
};
@@ -92,6 +94,8 @@ struct btmrvl_sdio_card {
struct btmrvl_sdio_device {
const char *helper;
const char *firmware;
+ const struct btmrvl_sdio_card_reg *reg;
+ u16 sd_blksz_fw_dl;
};