summaryrefslogtreecommitdiff
path: root/drivers/char/xillybus
diff options
context:
space:
mode:
authorEli Billauer <eli.billauer@gmail.com>2016-02-24 11:40:51 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-03-05 23:19:39 +0300
commitba327173ef48c12cf6f326441c74f373fa3be220 (patch)
treed026f0eb8411ea9c98b59271a4a06ebf0c3d5c1e /drivers/char/xillybus
parenta75fa128236bc2fdaa5e412145cbd577e42e14c2 (diff)
downloadlinux-ba327173ef48c12cf6f326441c74f373fa3be220.tar.xz
char: xillybus: Fix internal data structure initialization
A couple of fields in a data structure, which is used by the driver only, were not initialized properly during the driver's setup. The primary issue with this bug was that channel->wr_buf_size remained zero, so calls to dma_sync_single_for_cpu() took place with zero size, and consequently did nothing. This had a rather minimal practical impact, because (a) these calls are NOPs on Intel/AMD platforms, as well as other platforms with coherent cache, and (b) it's extremely rare that any cache line would survive between two reads from a given DMA buffer Hence no significant practical difference is expected with this patch. Signed-off-by: Eli Billauer <eli.billauer@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/char/xillybus')
-rw-r--r--drivers/char/xillybus/xillybus_core.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/char/xillybus/xillybus_core.c b/drivers/char/xillybus/xillybus_core.c
index 77d6c127e691..dcd19f3f182e 100644
--- a/drivers/char/xillybus/xillybus_core.c
+++ b/drivers/char/xillybus/xillybus_core.c
@@ -509,7 +509,7 @@ static int xilly_setupchannels(struct xilly_endpoint *ep,
channel->log2_element_size = ((format > 2) ?
2 : format);
- bytebufsize = channel->rd_buf_size = bufsize *
+ bytebufsize = bufsize *
(1 << channel->log2_element_size);
buffers = devm_kcalloc(dev, bufnum,
@@ -523,6 +523,7 @@ static int xilly_setupchannels(struct xilly_endpoint *ep,
if (!is_writebuf) {
channel->num_rd_buffers = bufnum;
+ channel->rd_buf_size = bytebufsize;
channel->rd_allow_partial = allowpartial;
channel->rd_synchronous = synchronous;
channel->rd_exclusive_open = exclusive_open;
@@ -533,6 +534,7 @@ static int xilly_setupchannels(struct xilly_endpoint *ep,
bufnum, bytebufsize);
} else if (channelnum > 0) {
channel->num_wr_buffers = bufnum;
+ channel->wr_buf_size = bytebufsize;
channel->seekable = seekable;
channel->wr_supports_nonempty = supports_nonempty;