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authorStephen Boyd <sboyd@kernel.org>2019-05-07 21:45:13 +0300
committerStephen Boyd <sboyd@kernel.org>2019-05-07 21:45:13 +0300
commit5816b74581b45cf086a84ab14e13354a65e8e22c (patch)
treebe2c3661aa11a6cb4aabd256f85ba308aad1ad32 /drivers/clk/Makefile
parent7e9c62bdb41af76974d594da89854a6aba645e58 (diff)
parent9f77a60669d13ed4ddfa6cd7374c9d88da378ffa (diff)
parent76c547830bd116dbadf9c4b3c04ce5bf4da6dfe9 (diff)
parent93737fe93ec6cd3ffe49f631ad854c36a3d78ac2 (diff)
parentd3dfc16f8fa10e026509130cd705fd7dc925c946 (diff)
parent42614b5bd9549747af5c5dbef59397b0423f1101 (diff)
downloadlinux-5816b74581b45cf086a84ab14e13354a65e8e22c.tar.xz
Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' and 'clk-qoriq' into clk-next
- Mark UFS clk as critical on Hi-Silicon hi3660 SoCs - Support for Cirrus Logic Lochnagar clks * clk-hisi: clk: hi3660: Mark clk_gate_ufs_subsys as critical * clk-lochnagar: clk: lochnagar: Add support for the Cirrus Logic Lochnagar clk: lochnagar: Add initial binding documentation * clk-allwinner: clk: sunxi-ng: sun5i: Export the MBUS clock clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate clk: sunxi-ng: h6: Preset hdmi-cec clock parent clk: sunxi: Add Kconfig options clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset clk: sunxi-ng: Allow DE clock to set parent rate * clk-rockchip: clk: rockchip: undo several noc and special clocks as critical on rk3288 clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288 clk: rockchip: Limit use of USB PHY clock to USB on rk3288 clk: rockchip: Fix video codec clocks on rk3288 clk: rockchip: Make rkpwm a critical clock on rk3288 clk: rockchip: fix wrong clock definitions for rk3328 * clk-qoriq: clk: qoriq: increase array size of cmux_to_group dt-bindings: qoriq-clock: Add ls1028a chip compatible string clk: qoriq: Add ls1028a clock configuration clk: qoriq: add more PLL divider clocks support dt-bindings: qoriq-clock: add more PLL divider clocks support