diff options
author | Paul Cercueil <paul@crapouillou.net> | 2021-05-30 19:49:21 +0300 |
---|---|---|
committer | Stephen Boyd <sboyd@kernel.org> | 2021-06-28 05:49:17 +0300 |
commit | 037f1ffd0f0a6bad89e17aa4698c97ef430c6ad1 (patch) | |
tree | a9bfcfae8cfa961c5caba6119ec444bd857be429 /drivers/clk/ingenic/cgu.h | |
parent | 315a8423b20362bb675c5263cb237ecb51d9589e (diff) | |
download | linux-037f1ffd0f0a6bad89e17aa4698c97ef430c6ad1.tar.xz |
clk: ingenic: Remove pll_info.no_bypass_bit
We can express that a PLL has no bypass bit by simply setting the
.bypass_bit field to a negative value.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net
Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic/cgu.h')
-rw-r--r-- | drivers/clk/ingenic/cgu.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 44d97a259692..10521d1b7b12 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -39,10 +39,10 @@ * their encoded values in the PLL control register, or -1 for * unsupported values * @bypass_reg: the offset of the bypass control register within the CGU - * @bypass_bit: the index of the bypass bit in the PLL control register + * @bypass_bit: the index of the bypass bit in the PLL control register, or + * -1 if there is no bypass bit * @enable_bit: the index of the enable bit in the PLL control register * @stable_bit: the index of the stable bit in the PLL control register - * @no_bypass_bit: if set, the PLL has no bypass functionality */ struct ingenic_cgu_pll_info { unsigned reg; @@ -52,10 +52,9 @@ struct ingenic_cgu_pll_info { u8 n_shift, n_bits, n_offset; u8 od_shift, od_bits, od_max; unsigned bypass_reg; - u8 bypass_bit; + s8 bypass_bit; u8 enable_bit; u8 stable_bit; - bool no_bypass_bit; }; /** |