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author | Paul Cercueil <paul@crapouillou.net> | 2021-05-30 19:49:19 +0300 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2021-06-28 05:49:17 +0300 |
commit | 249592bf6d5d52cacdc2f5a07f23368fc1b11324 (patch) | |
tree | 037c1a9a90e52d1d249d83c6996dd65214f92794 /drivers/clk/ingenic/cgu.h | |
parent | 2e1ae04f7fe049bb012c273e5281a3c145924ea1 (diff) | |
download | linux-249592bf6d5d52cacdc2f5a07f23368fc1b11324.tar.xz |
clk: Support bypassing dividers
When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU
code expects the mux to be applied first, the divider second.
On the JZ4760, and maybe on some other SoCs, some clocks also have a mux
setting and a divider, but the divider is not applied to all parents
selectable from the mux.
This could be solved by creating two clocks, one with CGU_CLK_DIV and
one with CGU_CLK_MUX, but that would increase the number of clocks.
Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit
corresponding to the parent clock's index is set, the divider is
bypassed.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic/cgu.h')
-rw-r--r-- | drivers/clk/ingenic/cgu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 2c75ef4a36f5..44d97a259692 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -84,6 +84,7 @@ struct ingenic_cgu_mux_info { * isn't one * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one + * @bypass_mask: mask of parent clocks for which the divider does not apply * @div_table: optional table to map the value read from the register to the * actual divider value */ @@ -95,6 +96,7 @@ struct ingenic_cgu_div_info { s8 ce_bit; s8 busy_bit; s8 stop_bit; + u8 bypass_mask; const u8 *div_table; }; |