diff options
| author | Aidan MacDonald <aidanmacdonald.0x0@gmail.com> | 2022-10-26 22:43:41 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-10-27 21:59:05 +0300 |
| commit | d84bf9d6308e2606b60bb5b4577f8b9ac295cf0b (patch) | |
| tree | 59d577cecc7305a7e1feb1842916614816b6442e /drivers/clk/ingenic/cgu.h | |
| parent | 83b975b5aa9522b6d72b2a8c0f3c209726ceb6b3 (diff) | |
| download | linux-d84bf9d6308e2606b60bb5b4577f8b9ac295cf0b.tar.xz | |
clk: ingenic: Make PLL clock enable_bit and stable_bit optional
When the enable bit is undefined, the clock is assumed to be always
on and enable/disable is a no-op. When the stable bit is undefined,
the PLL stable check is a no-op.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-3-aidanmacdonald.0x0@gmail.com
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic/cgu.h')
| -rw-r--r-- | drivers/clk/ingenic/cgu.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 567142b584bb..a5e44ca7f969 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -42,8 +42,10 @@ * @bypass_reg: the offset of the bypass control register within the CGU * @bypass_bit: the index of the bypass bit in the PLL control register, or * -1 if there is no bypass bit - * @enable_bit: the index of the enable bit in the PLL control register - * @stable_bit: the index of the stable bit in the PLL control register + * @enable_bit: the index of the enable bit in the PLL control register, or + * -1 if there is no enable bit (ie, the PLL is always on) + * @stable_bit: the index of the stable bit in the PLL control register, or + * -1 if there is no stable bit */ struct ingenic_cgu_pll_info { unsigned reg; @@ -54,8 +56,8 @@ struct ingenic_cgu_pll_info { u8 od_shift, od_bits, od_max; unsigned bypass_reg; s8 bypass_bit; - u8 enable_bit; - u8 stable_bit; + s8 enable_bit; + s8 stable_bit; void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, unsigned long rate, unsigned long parent_rate, unsigned int *m, unsigned int *n, unsigned int *od); |