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authorJerome Brunet <jbrunet@baylibre.com>2018-08-01 17:00:53 +0300
committerJerome Brunet <jbrunet@baylibre.com>2018-09-26 13:02:00 +0300
commitdd601dbc011e4eeda9e4c8c19ffe5b2fb33223dc (patch)
tree4a3ec158d243c98e47fdf5b11a50e2bf4483f69d /drivers/clk/meson/axg.c
parent87173557d2f6d28ba6e19f8aaf6b7f3d45d51511 (diff)
downloadlinux-dd601dbc011e4eeda9e4c8c19ffe5b2fb33223dc.tar.xz
clk: meson: clk-pll: drop hard-coded rates from pll tables
Putting hard-coded rates inside the parameter tables assumes that the parent is known and will never change. That's a big assumption we should not make. We have everything we need to recalculate the output rate using the parent rate and the rest of the parameters. Let's do so and drop the rates from the tables. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg.c')
-rw-r--r--drivers/clk/meson/axg.c73
1 files changed, 36 insertions, 37 deletions
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index a5e4f7b22f39..7511b3e26d40 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -134,36 +134,36 @@ static struct clk_regmap axg_sys_pll = {
},
};
-static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
- PLL_RATE(960000000, 40, 1),
- PLL_RATE(984000000, 41, 1),
- PLL_RATE(1008000000, 42, 1),
- PLL_RATE(1032000000, 43, 1),
- PLL_RATE(1056000000, 44, 1),
- PLL_RATE(1080000000, 45, 1),
- PLL_RATE(1104000000, 46, 1),
- PLL_RATE(1128000000, 47, 1),
- PLL_RATE(1152000000, 48, 1),
- PLL_RATE(1176000000, 49, 1),
- PLL_RATE(1200000000, 50, 1),
- PLL_RATE(1224000000, 51, 1),
- PLL_RATE(1248000000, 52, 1),
- PLL_RATE(1272000000, 53, 1),
- PLL_RATE(1296000000, 54, 1),
- PLL_RATE(1320000000, 55, 1),
- PLL_RATE(1344000000, 56, 1),
- PLL_RATE(1368000000, 57, 1),
- PLL_RATE(1392000000, 58, 1),
- PLL_RATE(1416000000, 59, 1),
- PLL_RATE(1440000000, 60, 1),
- PLL_RATE(1464000000, 61, 1),
- PLL_RATE(1488000000, 62, 1),
- PLL_RATE(1512000000, 63, 1),
- PLL_RATE(1536000000, 64, 1),
- PLL_RATE(1560000000, 65, 1),
- PLL_RATE(1584000000, 66, 1),
- PLL_RATE(1608000000, 67, 1),
- PLL_RATE(1632000000, 68, 1),
+static const struct pll_params_table axg_gp0_pll_params_table[] = {
+ PLL_PARAMS(40, 1),
+ PLL_PARAMS(41, 1),
+ PLL_PARAMS(42, 1),
+ PLL_PARAMS(43, 1),
+ PLL_PARAMS(44, 1),
+ PLL_PARAMS(45, 1),
+ PLL_PARAMS(46, 1),
+ PLL_PARAMS(47, 1),
+ PLL_PARAMS(48, 1),
+ PLL_PARAMS(49, 1),
+ PLL_PARAMS(50, 1),
+ PLL_PARAMS(51, 1),
+ PLL_PARAMS(52, 1),
+ PLL_PARAMS(53, 1),
+ PLL_PARAMS(54, 1),
+ PLL_PARAMS(55, 1),
+ PLL_PARAMS(56, 1),
+ PLL_PARAMS(57, 1),
+ PLL_PARAMS(58, 1),
+ PLL_PARAMS(59, 1),
+ PLL_PARAMS(60, 1),
+ PLL_PARAMS(61, 1),
+ PLL_PARAMS(62, 1),
+ PLL_PARAMS(63, 1),
+ PLL_PARAMS(64, 1),
+ PLL_PARAMS(65, 1),
+ PLL_PARAMS(66, 1),
+ PLL_PARAMS(67, 1),
+ PLL_PARAMS(68, 1),
{ /* sentinel */ },
};
@@ -207,7 +207,7 @@ static struct clk_regmap axg_gp0_pll_dco = {
.shift = 29,
.width = 1,
},
- .table = axg_gp0_pll_rate_table,
+ .table = axg_gp0_pll_params_table,
.init_regs = axg_gp0_init_regs,
.init_count = ARRAY_SIZE(axg_gp0_init_regs),
},
@@ -275,7 +275,7 @@ static struct clk_regmap axg_hifi_pll_dco = {
.shift = 29,
.width = 1,
},
- .table = axg_gp0_pll_rate_table,
+ .table = axg_gp0_pll_params_table,
.init_regs = axg_hifi_init_regs,
.init_count = ARRAY_SIZE(axg_hifi_init_regs),
.flags = CLK_MESON_PLL_ROUND_CLOSEST,
@@ -631,11 +631,10 @@ static struct clk_regmap axg_mpll3 = {
},
};
-static const struct pll_rate_table axg_pcie_pll_rate_table[] = {
+static const struct pll_params_table axg_pcie_pll_params_table[] = {
{
- .rate = 1600000000,
- .m = 200,
- .n = 3,
+ .m = 200,
+ .n = 3,
},
{ /* sentinel */ },
};
@@ -682,7 +681,7 @@ static struct clk_regmap axg_pcie_pll_dco = {
.shift = 29,
.width = 1,
},
- .table = axg_pcie_pll_rate_table,
+ .table = axg_pcie_pll_params_table,
.init_regs = axg_pcie_init_regs,
.init_count = ARRAY_SIZE(axg_pcie_init_regs),
},