clk: meson: pll: update driver for the g12a

The g12a use fractional parameter of 17 useful bits. At the moment, this
parameter in encoded using u16 value. Use this opportunity to switch all
the pll to parameter to unsigned int. This should save us some annoying
trouble shooting when and m and n field eventually grow as well.

This patch also introduce pll multiplier range. On the g12a, the hifi and
gp0 plls are able to lock as long as the following condition is met:
55 <= m/n <= 255.

The param table describing this would be huge which is a waste of memory.
Using ranges, we can save memory. Ranges also help find the best pll
parameter significantly faster since we don't have to try all the possible
settings.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[jbrunet: fixed fix pll settings calculation with arm32]
Link: https://lkml.kernel.org/r/20190201145345.6795-2-jbrunet@baylibre.com

1 files changed, 8 insertions, 2 deletions

diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
index 5ccf0854d932..55af2e285b1b 100644
--- a/drivers/clk/meson/clk-pll.h
+++ b/drivers/clk/meson/clk-pll.h
@@ -12,8 +12,13 @@
 #include "parm.h"
 
 struct pll_params_table {
-	u16		m;
-	u16		n;
+	unsigned int	m;
+	unsigned int	n;
+};
+
+struct pll_mult_range {
+	unsigned int	min;
+	unsigned int	max;
 };
 
 #define PLL_PARAMS(_m, _n)						\
@@ -34,6 +39,7 @@ struct meson_clk_pll_data {
 	const struct reg_sequence *init_regs;
 	unsigned int init_count;
 	const struct pll_params_table *table;
+	const struct pll_mult_range *range;
 	u8 flags;
 };