Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "I'm actually surprised this time. There aren't any new Qualcomm SoC
  clk drivers. And there's zero diff in the core clk framework.

  Instead we have new clk drivers for STM and Sophgo, with
  Samsung^WGoogle in third for the diffstat because they introduced HSI0
  and HSI2 clk drivers for Google's GS101 SoC (high speed interface
  things like PCIe, UFS, and MMC).

  Beyond those big diffs there's the usual updates to various clk
  drivers for incorrect parent descriptions or mising
  MODULE_DEVICE_TABLE()s, etc. Nothing in particular stands out as super
  interesting here.

  New Drivers:
   - STM32MP257 SoC clk driver
   - Airoha EN7581 SoC clk driver
   - Sophgo CV1800B, CV1812H and SG2000 SoC clk driver
   - Loongson-2k0500 and Loongson-2k2000 SoC clk driver
   - Add HSI0 and HSI2 clock controllers for Google GS101
   - Add i.MX95 BLK CTL clock driver

  Updates:
   - Allocate clk_ops dynamically for SCMI clk driver
   - Add support in qcom RCG and RCG2 for multiple configurations for
     the same frequency
   - Use above support for IPQ8074 NSS port 5 and 6 clocks to resolve
     issues
   - Fix the Qualcomm APSS IPQ5018 PLL to fix boot failures of some
     boards
   - Cleanups and fixes for Qualcomm Stromer PLLs
   - Reduce max CPU frequency on Qualcomm APSS IPQ5018
   - Fix Kconfig dependencies of Qualcomm SM8650 GPU and SC8280XP camera
     clk drivers
   - Make Qualcomm MSM8998 Venus clocks functional
   - Cleanup downstream remnants related to DisplayPort across Qualcomm
     SM8450, SM6350, SM8550, and SM8650
   - Reuse the Huayra APSS register map on Qualcomm MSM8996 CBF PLL
   - Use a specific Qualcomm QCS404 compatible for the otherwise generic
     HFPLL
   - Remove Qualcomm SM8150 CPUSS AHB clk as it is unused
   - Remove an unused field in the Qualcomm RPM clk driver
   - Add missing MODULE_DEVICE_TABLE to Qualcomm MSM8917 and MSM8953
     global clock controller drivers
   - Allow choice of manual or firmware-driven control over PLLs, needed
     to fully implement CPU clock controllers on Exynos850
   - Correct PLL clock IDs on ExynosAutov9
   - Propagate certain clock rates to allow setting proper SPI clock
     rates on Google GS101
   - Mark certain Google GS101 clocks critical
   - Convert old S3C64xx clock controller bindings to DT schema
   - Add new PLL rate and missing mux on Rockchip rk3568
   - Add missing reset line on Rockchip rk3588
   - Removal of an unused field in struct rockchip_mmc_clock
   - Amlogic s4/a1: add regmap maximum register for proper debugfs dump
   - Amlogic s4: add MODULE_DEVICE_TABLE() on pll and periph controllers
   - Amlogic pll driver: print clock name on lock error to help debug
   - Amlogic vclk: finish dsi clock path support
   - Amlogic license: fix occurence "GPL v2" as reported by checkpatch
   - Add PM runtime support to i.MX8MP Audiomix
   - Add DT schema for i.MX95 Display Master Block Control
   - Convert to platform remove callback returning void for i.MX8MP
     Audiomix
   - Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on Renesas
     R-Car V4M
   - Add interrupt controller (PLIC) clock and reset on Renesas RZ/Five
   - Prepare power domain support for Renesas RZ/G2L family members, and
     add actual support on Renesas RZ/G3S SoC
   - Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on Renesas
     R-Car V4M
   - Add additional constraints to Allwinner A64 PLL MIPI clock
   - Fix autoloading sunxi-ng clocks when build as a module"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (118 commits)
  clk: samsung: Don't register clkdev lookup for the fixed rate clocks
  clk, reset: microchip: mpfs: fix incorrect preprocessor conditions
  clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs
  clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
  clk: qcom: Fix SM_GPUCC_8650 dependencies
  clk: qcom: Fix SC_CAMCC_8280XP dependencies
  dt-bindings: clocks: stm32mp25: add access-controllers description
  clock, reset: microchip: move all mpfs reset code to the reset subsystem
  clk: samsung: gs101: drop unused HSI2 clock parent data
  clk: rockchip: rk3568: Add PLL rate for 724 MHz
  clk: rockchip: Remove an unused field in struct rockchip_mmc_clock
  dt-bindings: clock: fixed: Define a preferred node name
  clk: meson: s4: fix module autoloading
  clk: samsung: gs101: mark some apm UASC and XIU clocks critical
  clk: imx: imx8mp: Convert to platform remove callback returning void
  clk: imx: imx8mp: Switch to RUNTIME_PM_OPS()
  clk: bcm: rpi: Assign ->num before accessing ->hws
  clk: bcm: dvp: Assign ->num before accessing ->hws
  clk: samsung: gs101: add support for cmu_hsi2
  clk: samsung: gs101: add support for cmu_hsi0
  ...

1 files changed, 2 insertions, 90 deletions

diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c
index 22eab91a6712..28ec0da88cb3 100644
--- a/drivers/clk/microchip/clk-mpfs.c
+++ b/drivers/clk/microchip/clk-mpfs.c
@@ -4,12 +4,10 @@
  *
  * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
  */
-#include <linux/auxiliary_bus.h>
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <linux/slab.h>
 #include <dt-bindings/clock/microchip,mpfs-clock.h>
 #include <soc/microchip/mpfs.h>
 
@@ -361,93 +359,6 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c
 	return 0;
 }
 
-/*
- * Peripheral clock resets
- */
-
-#if IS_ENABLED(CONFIG_RESET_CONTROLLER)
-
-u32 mpfs_reset_read(struct device *dev)
-{
-	struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
-
-	return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR);
-}
-EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS);
-
-void mpfs_reset_write(struct device *dev, u32 val)
-{
-	struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
-
-	writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR);
-}
-EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS);
-
-static void mpfs_reset_unregister_adev(void *_adev)
-{
-	struct auxiliary_device *adev = _adev;
-
-	auxiliary_device_delete(adev);
-	auxiliary_device_uninit(adev);
-}
-
-static void mpfs_reset_adev_release(struct device *dev)
-{
-	struct auxiliary_device *adev = to_auxiliary_dev(dev);
-
-	kfree(adev);
-}
-
-static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data)
-{
-	struct auxiliary_device *adev;
-	int ret;
-
-	adev = kzalloc(sizeof(*adev), GFP_KERNEL);
-	if (!adev)
-		return ERR_PTR(-ENOMEM);
-
-	adev->name = "reset-mpfs";
-	adev->dev.parent = clk_data->dev;
-	adev->dev.release = mpfs_reset_adev_release;
-	adev->id = 666u;
-
-	ret = auxiliary_device_init(adev);
-	if (ret) {
-		kfree(adev);
-		return ERR_PTR(ret);
-	}
-
-	return adev;
-}
-
-static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
-{
-	struct auxiliary_device *adev;
-	int ret;
-
-	adev = mpfs_reset_adev_alloc(clk_data);
-	if (IS_ERR(adev))
-		return PTR_ERR(adev);
-
-	ret = auxiliary_device_add(adev);
-	if (ret) {
-		auxiliary_device_uninit(adev);
-		return ret;
-	}
-
-	return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev);
-}
-
-#else /* !CONFIG_RESET_CONTROLLER */
-
-static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
-{
-	return 0;
-}
-
-#endif /* !CONFIG_RESET_CONTROLLER */
-
 static int mpfs_clk_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -499,7 +410,7 @@ static int mpfs_clk_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	return mpfs_reset_controller_register(clk_data);
+	return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR);
 }
 
 static const struct of_device_id mpfs_clk_of_match_table[] = {
@@ -532,3 +443,4 @@ MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver");
 MODULE_AUTHOR("Padmarao Begari <padmarao.begari@microchip.com>");
 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
 MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+MODULE_IMPORT_NS(MCHP_CLK_MPFS);