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| author | Lubomir Rintel <lkundrak@v3.sk> | 2020-03-09 22:42:41 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-03-21 04:19:31 +0300 |
| commit | 5d34d0b32d6c13947b0aa890fc4c68f203491169 (patch) | |
| tree | ae0e1acb9a8efb2af010fde05fa44810b534b9f4 /drivers/clk/mmp/clk.c | |
| parent | 7de0b8b8b0508af5fed2f2a07e3abb6acac0c466 (diff) | |
| download | linux-5d34d0b32d6c13947b0aa890fc4c68f203491169.tar.xz | |
clk: mmp2: Add support for PLL clock sources
The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are
constant, but in fact they are configurable.
Add logic for obtaining the actual clock rates on MMP2 as well as MMP3.
There is no documentation for either SoC, but the "systemsetting" drivers
from Marvell GPL code dump provide some clue as far as MPMU registers on
MMP2 [1] and MMP3 [2] go.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp2_systemsetting.c
[2] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp3_systemsetting.c
A separate commit will adjust the clk-of-mmp2 driver.
Tested on a MMP3-based Dell Wyse 3020 as well as MMP2-based OLPC
XO-1.75 laptop.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-5-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mmp/clk.c')
| -rw-r--r-- | drivers/clk/mmp/clk.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/clk/mmp/clk.c b/drivers/clk/mmp/clk.c index ca7d37e2c7be..317123641d1e 100644 --- a/drivers/clk/mmp/clk.c +++ b/drivers/clk/mmp/clk.c @@ -176,6 +176,37 @@ void mmp_register_div_clks(struct mmp_clk_unit *unit, } } +void mmp_register_pll_clks(struct mmp_clk_unit *unit, + struct mmp_param_pll_clk *clks, + void __iomem *base, int size) +{ + struct clk *clk; + int i; + + for (i = 0; i < size; i++) { + void __iomem *reg = NULL; + + if (clks[i].offset) + reg = base + clks[i].offset; + + clk = mmp_clk_register_pll(clks[i].name, + clks[i].default_rate, + base + clks[i].enable_offset, + clks[i].enable, + reg, clks[i].shift, + clks[i].input_rate, + base + clks[i].postdiv_offset, + clks[i].postdiv_shift); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + continue; + } + if (clks[i].id) + unit->clk_table[clks[i].id] = clk; + } +} + void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id, struct clk *clk) { |