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authorStephen Boyd <sboyd@kernel.org>2020-10-20 21:47:02 +0300
committerStephen Boyd <sboyd@kernel.org>2020-10-20 21:47:02 +0300
commit97f2f490c1a46e5e2e80b5c423fe1f4e11b65ac1 (patch)
tree39530d077b0aca3a2e106ca0b28ef8a1c0227466 /drivers/clk/mmp
parent3ab9a54f76e76c3b282c61451269bd614cd6cf52 (diff)
parent3270ee14557b583e9aa852d1bb413fc71ce1f0e0 (diff)
parenta3947209d380cfcbd081597954fe6ee254e9681f (diff)
parente9501b975a9efb499f2ecbe3374d433b25c5b4f4 (diff)
parent9ba9ad8f5be0ff6af87ed23e4d872f4eb422b525 (diff)
parent6487649ee8b81d6c3a4eb7f17505f7fe397fdca3 (diff)
parent07c565b42a04f38c49c3b09f89917cdf282c4743 (diff)
downloadlinux-97f2f490c1a46e5e2e80b5c423fe1f4e11b65ac1.tar.xz
Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', 'clk-const' and 'clk-mmp2' into clk-next
* clk-semicolon: clk: meson: use semicolons rather than commas to separate statements clk: mvebu: ap80x-cpu: use semicolons rather than commas to separate statements clk: uniphier: use semicolons rather than commas to separate statements * clk-axi-clkgen: clk: axi-clkgen: Set power bits for fractional mode clk: axi-clkgen: Add support for fractional dividers * clk-qoriq: clk: qoriq: modify MAX_PLL_DIV to 32 * clk-baikal: clk: baikal-t1: Mark Ethernet PLL as critical * clk-const: clk: pxa: Constify static struct clk_ops * clk-mmp2: clk: mmp2: Fix the display clock divider base