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authorLauri Hintsala <lauri.hintsala@bluegiga.com>2012-07-04 14:49:54 +0400
committerShawn Guo <shawn.guo@linaro.org>2012-07-05 05:36:44 +0400
commit64e2bc41304726a5ca8a4d37754db69b88841ebf (patch)
tree766144e5e436090e0cab3f07182234b80a19d638 /drivers/clk/mxs
parent275d58025f8d59c493384e1e9660c9c5b7b28d2d (diff)
downloadlinux-64e2bc41304726a5ca8a4d37754db69b88841ebf.tar.xz
clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3
SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand the frequency fix for ref_io1 to get SSP2 and SSP3 to work. Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'drivers/clk/mxs')
-rw-r--r--drivers/clk/mxs/clk-imx28.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 365053f052cd..98624eec5dd4 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -112,11 +112,11 @@ static void __init clk_misc_init(void)
/*
* 480 MHz seems too high to be ssp clock source directly,
- * so set frac0 to get a 288 MHz ref_io0.
+ * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
*/
val = readl_relaxed(FRAC0);
- val &= ~(0x3f << BP_FRAC0_IO0FRAC);
- val |= 30 << BP_FRAC0_IO0FRAC;
+ val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
+ val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
writel_relaxed(val, FRAC0);
}