diff options
| author | Stephen Boyd <sboyd@kernel.org> | 2024-03-09 02:27:48 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2024-03-09 02:27:48 +0300 |
| commit | 27ec6a1919f41996be59ae5d247a6ce941facd2e (patch) | |
| tree | 5b6633324cd9df9eb75d8f2a95a8dbae15fdd047 /drivers/clk/qcom/gcc-sc7280.c | |
| parent | 6613476e225e090cc9aad49be7fa504e290dd33d (diff) | |
| parent | 7d474b43087aa356d714d39870c90d77fc6f1186 (diff) | |
| download | linux-27ec6a1919f41996be59ae5d247a6ce941facd2e.tar.xz | |
Merge tag 'qcom-clk-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson:
- Support for Display, TCSR, GPU, and Camera clock controllers for
Qualcomm's X1 Elite SoC
- Typo fixes in the IPQ5018 GCC driver
- Add "qdss_at" clk on Qualcomm IPQ6018, needed for WiFi
- Properly terminate frequency tables in different qcom clk drivers
- Add MDSS, crypto, and SDCC resets on Qualcomm MSM8953
- Add missing UFS CLKREF clks on Qualcomm SC8180X
- Avoid significant delays during boot by adding a softdep on rpmhpd to SDM845 gcc driver
- Add QUPv3 RCGS w/ DFS and video resets to Qualcomm SM8150 GCC driver
- Fix the custom GPU GX "do-nothing" method in the GDSC driver
- Add an external regulator to GX GDSC on SC8280XP GPU clk driver
- Switch display, GPU, video, and camera clock drivers to module_platform_driver()
- Set a longer delay for Venus resets on many Qualcomm SoCs
- Correct the GDSC wait times in the Qualcomm SDM845 display clk driver
- Remove the unused Qualcomm sc7180 modem clk driver
* tag 'qcom-clk-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (62 commits)
clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset
clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk'
clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk'
clk: qcom: camcc-x1e80100: Fix missing DT_IFACE enum in x1e80100 camcc
clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays
clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays
clk: qcom: camcc-sc8280xp: fix terminating of frequency table arrays
clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays
clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays
clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays
clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays
clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times
dt-bindings: clk: qcom: drop the SC7180 Modem subsystem clock controller
clk: qcom: drop the SC7180 Modem subsystem clock driver
clk: qcom: Use qcom_branch_set_clk_en()
clk: qcom: branch: Add a helper for setting the enable bit
clk: qcom: dispcc-sm8250: Make clk_init_data and pll_vco const
clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks
clk: qcom: gcc-msm8953: add more resets
clk: qcom: videocc-*: switch to module_platform_driver
...
Diffstat (limited to 'drivers/clk/qcom/gcc-sc7280.c')
| -rw-r--r-- | drivers/clk/qcom/gcc-sc7280.c | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 2b661df5de26..f45a8318900c 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -3453,18 +3453,14 @@ static int gcc_sc7280_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* - * Keep the clocks always-ON - * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK - * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004);/* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26028);/* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004);/* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x2701c);/* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x28004);/* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28014);/* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */ regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, |