diff options
| author | Adam Skladowski <a39.skl@gmail.com> | 2022-04-26 10:30:46 +0300 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-05-06 06:22:27 +0300 |
| commit | 24a8ed12aa00af135fe698061017042532aac5e5 (patch) | |
| tree | b9f0050ed63d653d9e36f0a4db366941b7e49fc6 /drivers/clk/qcom | |
| parent | 4ac7e878c15781286c043cff19ec88d82b8e2014 (diff) | |
| download | linux-24a8ed12aa00af135fe698061017042532aac5e5.tar.xz | |
clk: qcom: gcc-msm8976: Set floor ops for SDCC
Just like in case of other SoCs change SDCC1/SDCC2 ops
to floor to avoid overclocking controller.
This commit only sets SDCC1/SDCC2 which are used for EMMC/SDCARD.
Leave SDCC3 because on this platform it's mostly used for WIFI/BT chips,
like on Sony Loire familly devices.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220426073048.11509-2-a39.skl@gmail.com
Diffstat (limited to 'drivers/clk/qcom')
| -rw-r--r-- | drivers/clk/qcom/gcc-msm8976.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/qcom/gcc-msm8976.c b/drivers/clk/qcom/gcc-msm8976.c index a8b15814933e..5781a7bcecc6 100644 --- a/drivers/clk/qcom/gcc-msm8976.c +++ b/drivers/clk/qcom/gcc-msm8976.c @@ -1486,7 +1486,7 @@ static const struct clk_init_data sdcc1_apps_clk_src_8976v1_1_init = { .name = "sdcc1_apps_clk_src", .parent_data = gcc_parent_data_v1_1, .num_parents = ARRAY_SIZE(gcc_parent_data_v1_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }; static struct clk_rcg2 sdcc1_apps_clk_src = { @@ -1499,7 +1499,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .name = "sdcc1_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; @@ -1547,7 +1547,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .name = "sdcc2_apps_clk_src", .parent_data = gcc_parent_data_4_8, .num_parents = ARRAY_SIZE(gcc_parent_data_4_8), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; |