diff options
| author | Nikita Yushchenko <nikita.yoush@cogentembedded.com> | 2021-12-25 22:39:57 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-01-24 11:55:14 +0300 |
| commit | d843e61e0ea50ecf2fc9276c828ea3867867fd89 (patch) | |
| tree | d787424c7636e9b5c06de84a7e873ffdf7ac15ac /drivers/clk/renesas/r8a77995-cpg-mssr.c | |
| parent | 59a43fa2487bf8ac67a758c4e653ce3db16f86a9 (diff) | |
| download | linux-d843e61e0ea50ecf2fc9276c828ea3867867fd89.tar.xz | |
clk: renesas: r8a7799[05]: Add MLP clocks
Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.
Similar to other R-Car Gen3 SoC, exact information on the parents of MLP
clocks on E3 and D3 is not available. However, since the parents of
these clocks are not anyhow software-controllable, the only harm from
this is inexact information exported via debugfs. So just keep the
parent set in the same way as with other Gen3 SoCs.
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Link: https://lore.kernel.org/r/20211225193957.2195012-1-nikita.yoush@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a77995-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 7713cfd99c1d..525eef197fd9 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -160,6 +160,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { DEF_MOD("du1", 723, R8A77995_CLK_S1D1), DEF_MOD("du0", 724, R8A77995_CLK_S1D1), DEF_MOD("lvds", 727, R8A77995_CLK_S2D1), + DEF_MOD("mlp", 802, R8A77995_CLK_S2D1), DEF_MOD("vin4", 807, R8A77995_CLK_S1D2), DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2), DEF_MOD("imr0", 823, R8A77995_CLK_S1D2), |