diff options
| author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2022-04-25 09:41:58 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-29 13:08:36 +0300 |
| commit | 7f906eaa95f38fae24957e0bf61878d5cb3f8847 (patch) | |
| tree | 762cc20c37d4f9e910eb346b9989eba032058a34 /drivers/clk/renesas/r8a779f0-cpg-mssr.c | |
| parent | 5d33481f54758eb050473af0692a043c084ad581 (diff) | |
| download | linux-7f906eaa95f38fae24957e0bf61878d5cb3f8847.tar.xz | |
clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4
R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220425064201.459633-5-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a779f0-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a779f0-cpg-mssr.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 5ed5dab16a2d..c17ebe6b5992 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -143,23 +143,23 @@ static const unsigned int r8a779f0_crit_mod_clks[] __initconst = { * CPG Clock Data */ /* - * MD EXTAL PLL1 PLL2 PLL3 PLL5 PLL6 OSC + * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC * 14 13 (MHz) - * ---------------------------------------------------------------- - * 0 0 16 / 1 x200 x150 x200 x200 x134 /15 - * 0 1 20 / 1 x160 x120 x160 x160 x106 /19 + * ------------------------------------------------------------------------ + * 0 0 16 / 1 x200 x150 x200 n/a x200 x134 /15 + * 0 1 20 / 1 x160 x120 x160 n/a x160 x106 /19 * 1 0 Prohibited setting - * 1 1 40 / 2 x160 x120 x160 x160 x106 /38 + * 1 1 40 / 2 x160 x120 x160 n/a x160 x106 /38 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { - /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ - { 1, 200, 1, 150, 1, 200, 1, 200, 1, 134, 1, 15, }, - { 1, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 19, }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { 2, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 38, }, + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ + { 1, 200, 1, 150, 1, 200, 1, 0, 0, 200, 1, 134, 1, 15, }, + { 1, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 19, }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + { 2, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 38, }, }; static int __init r8a779f0_cpg_mssr_init(struct device *dev) |