diff options
| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2023-02-02 12:23:31 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-02-10 12:35:16 +0300 |
| commit | b1dec4e78599a2ce5bf8557056cd6dd72e1096b0 (patch) | |
| tree | d373ae3f7815740653366aafee1508428038c9c8 /drivers/clk/renesas/rcar-gen3-cpg.c | |
| parent | bd176e46e9c23f669b28630cc8f3fb1b89fd610e (diff) | |
| download | linux-b1dec4e78599a2ce5bf8557056cd6dd72e1096b0.tar.xz | |
clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
R-Car H3 ES1.* was only available to an internal development group and
needed a lot of quirks and workarounds. These become a maintenance
burden now, so our development group decided to remove upstream support
for this SoC. Public users only have ES2 onwards.
In addition to the ES1 specific removals, a check for it was added
preventing the machine to boot further. It may otherwise inherit wrong
clock settings from ES2 which could damage the hardware.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230202092332.2504-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.c')
| -rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.c | 17 |
1 files changed, 2 insertions, 15 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index e668f23c75e7..b3ef62fa612e 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -310,20 +310,11 @@ static unsigned int cpg_clk_extalr __initdata; static u32 cpg_mode __initdata; static u32 cpg_quirks __initdata; -#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ static const struct soc_device_attribute cpg_quirks_match[] __initconst = { { - .soc_id = "r8a7795", .revision = "ES1.0", - .data = (void *)(PLL_ERRATA | RCKCR_CKSEL), - }, - { - .soc_id = "r8a7795", .revision = "ES1.*", - .data = (void *)(RCKCR_CKSEL), - }, - { .soc_id = "r8a7796", .revision = "ES1.0", .data = (void *)(RCKCR_CKSEL), }, @@ -355,9 +346,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, * multiplier when cpufreq changes between normal and boost * modes. */ - mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2; return cpg_pll_clk_register(core->name, __clk_get_name(parent), - base, mult, CPG_PLL0CR, 0); + base, 2, CPG_PLL0CR, 0); case CLK_TYPE_GEN3_PLL1: mult = cpg_pll_config->pll1_mult; @@ -370,9 +360,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, * multiplier when cpufreq changes between normal and boost * modes. */ - mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2; return cpg_pll_clk_register(core->name, __clk_get_name(parent), - base, mult, CPG_PLL2CR, 2); + base, 2, CPG_PLL2CR, 2); case CLK_TYPE_GEN3_PLL3: mult = cpg_pll_config->pll3_mult; @@ -388,8 +377,6 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, */ value = readl(base + CPG_PLL4CR); mult = (((value >> 24) & 0x7f) + 1) * 2; - if (cpg_quirks & PLL_ERRATA) - mult *= 2; break; case CLK_TYPE_GEN3_SDH: |