diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2022-09-07 19:01:56 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2022-09-13 13:09:14 +0300 |
| commit | 30d8b7d43c840f5907c0e688d41093f176ba8ac1 (patch) | |
| tree | 820fd500c4add2d430e5d1b804aadde51f16f071 /drivers/clk/rockchip/clk.h | |
| parent | 1c23f9e627a7b412978b4e852793c5e3c3efc555 (diff) | |
| download | linux-30d8b7d43c840f5907c0e688d41093f176ba8ac1.tar.xz | |
clk: rockchip: Add MUXTBL variant
Add a clock branch consisting of a mux with non-standard
select values. The parent in Mux table is sorted by priority.
Use clk_register_mux_table() to register such a mux-clock.
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20220907160207.3845791-3-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 7aa45cc70287..93937fb1d368 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -448,6 +448,7 @@ struct rockchip_clk_branch { u8 mux_shift; u8 mux_width; u8 mux_flags; + u32 *mux_table; int div_offset; u8 div_shift; u8 div_width; @@ -680,6 +681,22 @@ struct rockchip_clk_branch { .gate_offset = -1, \ } +#define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \ + { \ + .id = _id, \ + .branch_type = branch_mux, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = o, \ + .mux_shift = s, \ + .mux_width = w, \ + .mux_flags = mf, \ + .gate_offset = -1, \ + .mux_table = mt, \ + } + #define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \ { \ .id = _id, \ |