diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2022-10-18 18:14:03 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2022-11-14 17:33:46 +0300 |
| commit | 8f6594494b1cb0ad14493795b436413cfe64a0f8 (patch) | |
| tree | 3e5b6f243dc2fd8821175c98a54251d1146a772c /drivers/clk/rockchip/clk.h | |
| parent | cf87691f143e6cc5727767b02ec2be3725534a5d (diff) | |
| download | linux-8f6594494b1cb0ad14493795b436413cfe64a0f8.tar.xz | |
clk: rockchip: add pll type for RK3588
Add RK3588 PLL support fully relying on lookup tables like
the other upstream supported rockchip platforms.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[rebase and modify code to avoid PLL parameter calculation]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-6-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 43a37a43b6f3..6eb31d36c4cd 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -240,6 +240,8 @@ enum rockchip_pll_type { pll_rk3066, pll_rk3328, pll_rk3399, + pll_rk3588, + pll_rk3588_core, }; #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ @@ -272,6 +274,15 @@ enum rockchip_pll_type { .nb = _nb, \ } +#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ +{ \ + .rate = _rate##U, \ + .p = _p, \ + .m = _m, \ + .s = _s, \ + .k = _k, \ +} + /** * struct rockchip_clk_provider - information about clock provider * @reg_base: virtual address for the register base. @@ -307,6 +318,13 @@ struct rockchip_pll_rate_table { unsigned int dsmpd; unsigned int frac; }; + struct { + /* for RK3588 */ + unsigned int m; + unsigned int p; + unsigned int s; + unsigned int k; + }; }; }; |