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| author | Elaine Zhang <zhangqing@rock-chips.com> | 2022-10-18 18:14:02 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2022-11-14 17:33:45 +0300 |
| commit | cf87691f143e6cc5727767b02ec2be3725534a5d (patch) | |
| tree | f5530ec60fe2a2a6df7b248ea1c7942252a21d64 /drivers/clk/rockchip/clk.h | |
| parent | 4f5ca304f202938a07eb0c2e20551795286d817d (diff) | |
| download | linux-cf87691f143e6cc5727767b02ec2be3725534a5d.tar.xz | |
clk: rockchip: add register offset of the cores select parent
The cores select parent register is special on RK3588.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-5-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index ee01739e4a7c..43a37a43b6f3 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -389,6 +389,8 @@ struct rockchip_cpuclk_rate_table { * @div_core_shift[]: cores divider offset used to divide the pll value * @div_core_mask[]: cores divider mask * @num_cores: number of cpu cores + * @mux_core_reg: register offset of the cores select parent + * @mux_core_alt: mux value to select alternate parent * @mux_core_main: mux value to select main parent of core * @mux_core_shift: offset of the core multiplexer * @mux_core_mask: core multiplexer mask @@ -398,6 +400,7 @@ struct rockchip_cpuclk_reg_data { u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES]; u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES]; int num_cores; + int mux_core_reg; u8 mux_core_alt; u8 mux_core_main; u8 mux_core_shift; |