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author | Stephen Boyd <sboyd@kernel.org> | 2023-04-25 21:52:25 +0300 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2023-04-25 21:52:25 +0300 |
commit | c19c6c7b44c69faa7a18ef79e758f580b144fd8f (patch) | |
tree | 148c11c2e11565cf9afd55fed421d21d0a3b51d3 /drivers/clk/rockchip | |
parent | 1a86e99fa00a6284c9419043493246d38ad3357f (diff) | |
parent | 27a6e1b09a782517fddac91259970ac466a3f7b6 (diff) | |
parent | ef382228d25a93aa9dcb8be6e82322c272831cda (diff) | |
parent | 0818c8d46948da430e41eb426b54f061b5d03bf0 (diff) | |
parent | ea90f303e8c195f0cbb25b5df21d203d2bb503e0 (diff) | |
download | linux-c19c6c7b44c69faa7a18ef79e758f580b144fd8f.tar.xz |
Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next
* clk-of:
clk: add missing of_node_put() in "assigned-clocks" property parsing
* clk-samsung:
clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical
clk: samsung: Convert to platform remove callback returning void
clk: samsung: exynos5433: Extract PM support to common ARM64 layer
clk: samsung: Extract parent clock enabling to common function
clk: samsung: Extract clocks registration to common function
clk: samsung: exynos850: Add AUD and HSI main gate clocks
clk: samsung: exynos850: Implement CMU_G3D domain
clk: samsung: clk-pll: Implement pll0818x PLL type
clk: samsung: Set dev in samsung_clk_init()
clk: samsung: Don't pass reg_base to samsung_clk_register_pll()
clk: samsung: Remove np argument from samsung_clk_init()
dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
* clk-rockchip:
clk: rockchip: rk3588: make gate linked clocks critical
clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent
* clk-qcom: (57 commits)
clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
clk: qcom: add the GPUCC driver for sa8775p
dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc
clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`
clk: qcom: Add Global Clock Controller driver for IPQ9574
dt-bindings: clock: Add ipq9574 clock and reset definitions
clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value
clk: qcom: gcc-sm6115: Mark RCGs shared where applicable
clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset
dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset
clk: qcom: apss-ipq-pll: add support for IPQ5332
dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible
clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types
dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match
dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks
...